Method of forming shallow trench isolation

Details Method of forming shallow trench isolation Method of forming shallow trench isolation

1998-12-04

2001-07-31

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S296000, C438S427000, C257S397000, C257S510000

Reexamination Certificate

active

06268264

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority benefit of Taiwan application Ser. No. 87117381, filed Oct. 21, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of forming an integrated circuit, and more particularly, to a method of forming a shallow trench isolation (STI).
2. Description of the Related Art
In the very advanced fabrication technology of integrated circuits, to reduce the dimensions of devices and to increase the integration are a leading trend and topic for further development. However, as the dimensions of devices shrink the isolation structures between devices have to shrink as well. It is thus to cause a problem and difficulty in fabrication. Isolation structure such as a field oxide formed by local oxidation (LOCOS) has been widely used in the conventional fabrication process. Due to the consequently caused characteristics such as a bird's beak, this technique cannot meet the requirement for high integration. Other structure such as a shallow trench isolation has been used instead of the field oxide layer, especially in sub-half micron fabrication process.
To fabricate a shallow trench isolation, a nitride layer is commonly used as a hard mask layer on a substrate. Using anisotropic etching, a trench is formed in the substrate. An oxide plug is then filled in the trench to form the shallow trench isolation. In the conventional method, it is inevitable that a recess occurs around the edge of the oxide plug to cause a corner effect. In the subsequent process, such as using ion implantation to form a source/drain region of a transistor in the substrate, the implanted charged ions would accumulate in the recess around edge. An abnormal subthreshold current is caused in a channel region of the transistor due to accumulated charges. That is, a kink effect is caused. The corner effect has been further discussed by Geissler, Poth, Lasky, Johnson, and Voldman in the paper “A New Three-Dimensional MOSFET Gate-Induced Drain Leakage Effect in Narrow Deep Submicron Device” published in IEEE IEDM Technical Digest, 1911.
To solve the problem of corner effect, Fazan and Pierre C. disclosed a method for fabricating a shallow trench isolation in U.S. Pat. No. 5,799,383. In this disclosure, after the formation of an oxide plug, an oxide layer is formed to cover the substrate and the oxide plug. Using wet etching, a pad oxide layer previously formed on the substrate is removed. However, it is known that the step of etching back the oxide layer is performed by a dry plasma etching process. Since the materials of the oxide layer and the pad oxide layer are apparently the same, the selectivity between these two layers for dry etching is so low that there is no effective way to control the etching level. As a consequence, the pad oxide layer is consequently removed while etching back the oxide layer. The substrate is very likely to be exposed under a plasma environment to be damaged by the plasma. Moreover, in the subsequently process such as an ion implantation, the substrate is directly exposed to the high energy implanted ions. The substrate is thus further damaged. Therefore, though this technique disclosed here improve the corner effect, the substrate is easily damaged by directly exposed under a plasma or implanted ions.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a method of fabricating a shallow trench isolation. The problem caused by the corner effect are solved, and the substrate is protected from being damaged.
To achieve the above-mentioned objects and advantages, a method of fabricating a shallow trench isolation is provided. A pad oxide layer is formed on a substrate. A hard mask layer is formed on the pad oxide layer. A trench is formed in the substrate and penetrating through the pad oxide and the hard mask layer. The trench is filled with an oxide plug. The hard mask layer is removed, so that the oxide plug has an upper portion protruding out of the substrate. A silicon thin film is formed to cover the oxide plug and the substrate. The silicon thin film is etched back by plasma dry etching to leave a spacer on a side wall of the protruding upper portion of the oxide plug. Using thermal oxidation, the spacer is oxidized into an oxide spacer, so that a shallow trench isolation is formed without the formation of a recess around the edge.
According to the invention, since the silicon thin film and the oxide layer have obviously different etching rates for dry etching, the pad oxide layer can be used as an etching stop for the etching back process without being removed consequently. With the protection of the pad oxide layer, the substrate is not directly under the attack of the etching plasma. In another aspect, with the formation of the spacer, the problems caused by recessed surface around the edge of the shallow trench isolation are eliminated. Furthermore, the pad oxide further protect the substrate from being damaged during the subsequent process such as ion implantation.


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JD 322100 A Abstracts of Research Disclosure Kenneth Masons Publications, Industrial Opportunites, 1991.

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