Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1998-04-09
2000-05-02
Bowers, Charles
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438296, 438246, 438359, H01L 2176
Patent
active
060572086
ABSTRACT:
A method of forming a shallow trench isolation structure is disclosed. A dielectric layer deposited by chemical vapor deposition is used as a sacrificial layer instead of conventional sacrificial oxide layer formed by thermal oxidation. Therefore, the oxide in the trench is further protected and less damaged.
REFERENCES:
patent: 5316965 (1994-05-01), Philipossain et al.
patent: 5728621 (1998-03-01), Zheng et al.
patent: 5733383 (1998-03-01), Fazan et al.
patent: 5960298 (1999-09-01), Kim
Stanley Wolf Silicon Processing for the VLSI Era vol. 3 Lattice Press p. 345, 1995.
S. M. Sze VLSI Technology McGraw Hill Book Company p. 268, 1988.
Huang Heng-Sheng
Lin Tony
Blum David S
Bowers Charles
United Microelectronics Corp.
LandOfFree
Method of forming shallow trench isolation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming shallow trench isolation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming shallow trench isolation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1593356