Method of forming separating region of semiconductor device

Details Method of forming separating region of semiconductor device Method of forming separating region of semiconductor device

1998-11-20

2001-01-30

Zarabian, Amir (Department: 2824)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S445000, C438S696000

Reexamination Certificate

active

06180488

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device and, more particularly, to a method of forming a separating region of a semiconductor device.
2. Background of the Related Art
For integrated circuit development of semiconductor devices, various methods to minimize the size of a device separating region and an active region or device forming region have been developed. LOCal Oxidation of Silicon (LOCOS) is one common method of forming a device separating region because of the simplicity and high reproducibility of the LOCOS process.
The separating oxide layer formed by the LOCOS, however, has its own “bird's beak” problem. The “bird's beak” occurs at the edge of a separating oxide layer and extends to the active region, which decreases the active region size. Thus, LOCOS is not suitable for a use in a Dynamic Random Access Memory (DRAM) device greater than 64 MB.
For 64 MB or 256 MB DRAMs, an advanced LOCOS technique has been developed to form a separating region. In the advanced LOCOS technique, the bird's beak is prevented or removed to reduce the separating region but increase the active region. However, the characteristic of such advanced LOCOS technique separating regions can deteriorate in DRAMs of greater than gigabytes, which must have the cell region less than 0.2 &mgr;m
2
in area. Since the advanced LOCOS separating region occupies much space and the field oxide layer is in contact with the silicon substrate, the concentration of the silicon substrate is reduced with a consequence of leakage current.
For DRAMs greater than gigabytes, there has been disclosed a method of forming the separating region by using a trench. The trench separating region permits easy regulation of the separating region thickness and a high efficiency of separation.
A method of forming a separating region of a related art semiconductor device will now be described.
FIG. 1
is a plan view of a related art semiconductor device.
As shown in
FIG. 1
, active and field regions are defined in a semiconductor device
11
. In the active region, separating layers
17
a
are each formed extending in the same direction at regular intervals. Gate electrodes
20
extend in a direction perpendicular to the device separating layers
17
a
to cross at predetermined intervals. Further, voids
18
formed on the surface of the device separating layers
17
a
are filled with conductive layers, which are used in forming a gate electrode, and connect adjacent gate electrodes
20
so that a current can flow there between.
FIGS. 2
a
-
2
g
are cross-sectional views along the line IV—IV of
FIG. 1
that illustrate a method of forming a separating region of the related art semiconductor device. As shown in
FIG. 2
a
, there are sequentially formed a first oxide layer
12
and a nitride layer
13
on silicon the substrate
11
. A photo resist
14
is then deposited and patterned on the nitride layer
13
.
As shown in
FIG. 2
b
, using the patterned photo resist
14
as a mask, the nitride layer
13
and the first silicon oxide layer
12
are selectively etched. Patterns
13
a
and
12
a
of the nitride layer
13
and the first silicon oxide layer
12
are respectively formed to define field and active regions. The active region is defined where the patterns
13
a
and
12
a
of the nitride layer
13
and the first silicon oxide layer
12
remain, while the field region is defined where the patterns
13
a
and
12
a
are eliminated.
As shown in
FIG. 2
c
, following removal of the photo resist
14
, the field region of the silicon substrate
11
is anisotropically etched to a defined depth. The anisotropic etching uses the pattern
13
a
of the nitride layer
13
as a mask to form a plurality of trenches
15
. The trenches
15
have sharp side angles.
As shown in
FIG. 2
d
, an oxidation is conducted on the silicon substrate
11
including the trenches
15
to form a second silicon oxide layer
16
on the trenches
15
. As shown in
FIG. 2
e
, a High Density Plasma (HDP) oxide layer
17
is formed on the whole surface of the silicon substrate
11
including the trenches
15
. The side angles of the trenches
15
are so steep that voids
18
are produced in the trenches
15
in the step of forming the HDP oxide layer
17
.
As shown in
FIG. 2
f
, the HDP oxide layer
17
is subjected to Chemical Mechanical Polishing (CMP) to have the surface of the pattern
13
a
of the nitride layer
13
exposed. In this manner, device separating layers
17
a
inside the trenches
15
are formed. On the surface of the device separating layers
17
a
, however, the voids
18
are exposed.
As shown in
FIG. 2
g
, following removal of the patterns
13
a
and
12
a
of the nitride layer
13
and the first silicon oxide layer
12
, a gate insulating layer
19
and a conductive layer for gate electrode (not shown) are formed on the whole surface of the silicon substrate
11
. The gate insulating layer
19
and the conductive layer are selectively etched to form a gate electrode
20
. The gate electrode
20
is partly overlapped with and perpendicular to the device separating layers
17
a
, and the gate insulating layer
19
is disposed on the active region of the silicon substrate.
The method of forming the separating region of the related art semiconductor device has several disadvantages. Voids occur inside the separating region trenches during a deposition of the insulating layer because of sharp side angles of the trenches. The voids permit current flow between the gate electrodes, which should be isolated from each other, resulting in failures of a device. Further, the gate insulating layer disposed in the contact region between the device separating layers and the silicon substrate may be eliminated in a subsequent cleaning step, which exposes the silicon substrate and leads to deterioration of the gate insulating layer reliability.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of forming a separating region of a semiconductor device that substantially obviates one or more of the problems caused by limitations and disadvantages of the related art.
Another object of the present invention is to provide a method of forming a separating region of a semiconductor device that increases device reliability.
Another object of the present invention is to provide a method for forming a separating region of a semiconductor device that prevents void formation in the field region.
Another object of the present invention is to provide a method for forming a separating region of a semiconductor device that increases reliability of the gate insulating layer.
Another object of the present invention is to provide a method for forming a separating region of a semiconductor device that prevents current flow between gate electrodes of gigabyte or higher DRAMS.
To achieve at least these objects and other advantages in a whole or in parts and in accordance with the purpose of the present invention, as embodied and broadly described, a method of forming a separating region of a semiconductor device includes forming a first insulating layer on a semiconductor substrate, selectively removing the first insulating layer to form a pattern having at least one opening in a prescribed region of the semiconductor substrate, forming side walls of a second insulating layer on sides of the first insulating layer pattern, removing the side walls of the second insulating layer and the semiconductor substrate using the first insulating layer pattern as a mask to form trenches in the semiconductor substrate, forming a third insulating layer on the first insulating layer pattern to fill the trenches and selectively removing the third insulating layer to expose an upper surface of the first insulating layer pattern to form a device separating layer.
To further achieve

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