Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1997-12-16
2002-06-11
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S713000, C438S714000, C438S719000
Reexamination Certificate
active
06403487
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor fabrication technologies, and more particularly, to a method of forming separated spacer structures in mixed-mode integrated circuits through a two-step etching process.
2. Description of Related Art
A mixed-mode integrated circuit is an integrated circuit in which at least two kinds of semiconductor devices with different purposes are provided. For instance, an integrated circuit having a memory device and a logic device integrated therein is a mixed-mode integrated circuit. Conventional mixed-mode integrated circuits include embedded dynamic random access memory (embedded DRAM), embedded static random access memory (SRAM), and application-specific integrated circuit (ASIC), to name a few. In accordance with the IC design rule, the various kinds of semiconductor devices in a mixed-mode integrated circuit should be applied with different operating voltages to the respective gates thereof. For instance, for a first kind of semiconductor device having a gate oxide layer of thickness 50 Å (angstrom) and a gate of thickness 0.25 &mgr;m (micrometer), the gate voltage applied thereto is about 2.5 V (volt); for a second kind of semiconductor device having a gate oxide layer of thickness 70 Å and a gate of thickness 0.34 &mgr;m, the gate voltage applied thereto is about 3.3 V; and for a third kind of semiconductor device having a gate oxide layer of thickness 130 Å and a gate of thickness 0.5 &mgr;m, the gate voltage applied thereto is about 5 V.
In a mixed-mode integrated circuit, each of the various kinds of semiconductor devices has its own unique spacer structure with a different spacer width from others for the purpose of providing a suitable channel resistance. An overly small spacer width would cause an overly strong electric field between source and drain, which can cause such undesired problems as hot-carrier problem or short-channel problem that would raise the reliability issue to the associated device. By contrast, an overly large spacer width would cause the problem of an insufficient driving current between source and drain. Conventional semiconductor fabrication technologies, however, fail to provide a suitable method that can be used to form spacers with different widths for the various kinds of devices in a mixed-mode integrated circuit.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method for forming separated spacer structures in a mixed-mode integrated circuit, which can be used to form spacer structures with different widths for the various kinds of devices in the mixed-mode integrated circuit.
In accordance with the foregoing and other objectives of the present invention, a method for forming separated spacer structures in a mixed-mode integrated circuit is provided. Two preferred embodiments of the method of the invention are disclosed.
The first preferred embodiment of the method of the invention includes the following procedural steps of:
(1) preparing a semiconductor substrate which is formed with at least a first gate for the first kind of device of the mixed-mode integrated circuit and a second gate for the second kind of device of the mixed-mode integrated circuit;
(2) forming an insulating layer which covers both of the first gate and the second gate;
(3) forming a first etching mask which covers a first surface area of the insulating layer that is located above the second gate while exposing a second surface area of the insulating layer that is located above the first gate;
(4) performing a first etching process on the insulating layer using the first etching mask so as to remove part of the insulating layer until the insulating layer, having a first remaining part of a first desired width and serving as a first spacer structure is left on the sidewalls of the first gate; then removing the first etching mask;
(5) forming a second etching mask which covers the first gate and the first spacer structure while exposing a surface area of the insulating layer above the second gate; and
(6) performing a second etching process on the insulating layer using the second etching mask so as to remove part of the insulating layer until the insulating layer, having a second remaining part of a second predetermined width; and serving as a second spacer structure is left on the sidewalls of the second gate, the second predetermined width, being different than the first predetermined width then removing the second etching mask.
The second preferred embodiment of the method of the invention includes the following procedural steps of:
(1) preparing a semiconductor substrate which is formed with at least a first gate for the first kind of device of the mixed-mode integrated circuit and a second gate for the second kind of device of the integrated circuit, the second gate being larger in width than the first gate, the first gate being formed with a first spacer structure, having a first predetermined width, on the sidewalls thereof while the second gate is to be formed with a second spacer structure, having a predetermined width, on the sidewalls thereof, the second predetermined width being larger than the first predetermined width;
(2) forming an insulating layer which covers both of the first gate and the second gate;
(3) performing a first etching process on the insulating layer so as to remove part of the insulating layer until a first remaining part and a second remaining part serving respectively as the first spacer structure and the second spacer structure are left on the sidewalls of the first gate and the second gate, respectively, the first and second spacer structures being etched to the second predetermined width;
(4) forming an etching mask which covers the second gate and the second spacer structure while exposing the first gate and the first spacer structure; and
(5) performing a second etching process on the first spacer structure using the etching mask so as to further remove a surface part of the first spacer structure until the width of the first spacer structure is reduced to the first predetermined width; then removing the second etching mask.
Through the foregoing steps, two spacer structures with different widths for the various kinds of devices in the same integrated circuit can be made.
REFERENCES:
patent: 5770493 (1998-06-01), Fulford, Jr.
patent: 5827761 (1998-10-01), Fulford, Jr. et al.
Chen Po-Hung
Hsu Cheng-Jung
Huang Cheng-Han
Tsai Meng-Jin
Perez Ramo Vanessa
United Microelectronics Corp.
Utech Benjamin L.
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