Method of forming semiconductor transistor devices

Details Method of forming semiconductor transistor devices Method of forming semiconductor transistor devices

1993-12-21

1995-02-21

Fourson, George

Fishing, trapping, and vermin destroying

437 35, 437 44, 437242, 437968, 257336, H01L 21265

Patent

active

053915089

ABSTRACT:
A method of forming semiconductor devices comprising the steps of forming, by restriction in the increased number of steps by a process close to the normal process, a field effect transistor having a local shallow source/drain diffusion layer on both the sides of a gate electrode for self-matching operation and without etching damages, wherein impurities are ion-implanted onto the semiconductor side wall and onto the substrate surface of both the sides, and thermal treatment operation is effected so as to form the local shallow source/drain diffusing layers by the diffusion for activating the impurities of the deep shallow source drain diffusing layers, thereby to render to be capable of restraining a short channel effect and reducing the parasitic resistance of the semiconductor devices.

REFERENCES:
patent: 5073514 (1991-12-01), Ito et al.
patent: 5089435 (1992-02-01), Akiyama
patent: 5145798 (1992-09-01), Smayling et al.
"Deep Submicron NMOSFETs Using Novel Locally Elevated Drain (LED) and Silicided LED (SLED) Structure", by S. Kakimoto et al, The Drafted Thesis for the 54th Applied Physics Institution Science Lecture in Autumn, 1993; Sep. 27-30, 1993; p. 727; published by Hokkaido University.

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