Method of forming semiconductor structure isolation regions

Details Method of forming semiconductor structure isolation regions Method of forming semiconductor structure isolation regions

1988-03-24

1989-10-24

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 33, H01L 2176

Patent

active

048762172

ABSTRACT:
A planarized dielectric isolation region for semiconductor devices and integrated circuits is created by providing a semiconductor substrate, providing on the substrate an oxide
itride mask with an opening for defining the isolation region and a closed portion for defining the desired semiconductor islands, anisotropically etching a trench into the semiconductor substrate, isotropically etching the substrate so as to slightly undercut the oxide
itride mask, thermally oxidizing the substrate to form a thin oxide layer on the bottom and sidewall of the trench wherein the outer surface of the thermal oxide approximately lines up with the edge of the oxide
itride mask at the top of the trench sidewall, filling the trench with a conformal deposited material (preferably a dielectric), providing a mask over the conformal material which is the complement to the trench etch or island mask but of smaller lateral dimensions so as to cover those portions of the conformal layer which do not rise up over the semiconductor island, etching away the exposed portions of the conformal material to a level approximately co-planar with the island surface and the portion of the conformal material under the mask, and removing the mask.

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