Method of forming semiconductor package

Details Method of forming semiconductor package Method of forming semiconductor package

2008-09-22

2010-06-29

Kebede, Brook (Department: 2894)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C257SE33066

Reexamination Certificate

active

07745260

ABSTRACT:
A method of forming a semiconductor package (10) including forming a plurality of cavities (14) in a substrate (12). An electrically conductive pattern (16) is formed on the substrate (12) and over the cavities (14). An electrically insulating layer (22) is formed over the substrate (12) and the electrically conductive pattern (16). A plurality of vias (24) is formed in the electrically insulating layer (22). An integrated circuit (IC) die (28) is attached to the electrically insulating layer (22) and electrically connected to the vias (24) such that the IC die (28) is connected to the electrically conductive pattern (16). A molding operation is performed to encapsulate the IC die (28). The substrate (12) is removed such that the electrically conductive pattern (16) is exposed.

REFERENCES:
patent: 4259436 (1981-03-01), Tabuchi
patent: 6100112 (2000-08-01), Amano
patent: 6344688 (2002-02-01), Wang
patent: 6911729 (2005-06-01), Chikawa
patent: 7315086 (2008-01-01), Kim
patent: 2002/0000829 (2002-01-01), Akram et al.
patent: 2008/0199980 (2008-08-01), Okayama

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