Method of forming semiconductor memory device

Details Method of forming semiconductor memory device Method of forming semiconductor memory device

1998-01-15

2001-04-17

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S255000, C438S398000

Reexamination Certificate

active

06218257

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method of forming a semiconductor memory device, and more particularly, the present invention relates to a method of forming a capacitor.
This application is a counterpart of Japanese application Serial Number 039616/1997, filed Feb. 25, 1997, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
FIG. 4
is a cross sectional view showing a one-bit memory cell of a conventional DRAM (Dynamic Random Access Memory), the one bit memory cell having a switching transistor, a capacitor, a bit line and a word line. The switching transistor includes a gate oxide layer
105
, a gate electrode
106
and a pair of n-type impurity regions
107
. The capacitor includes a storage electrode
116
,
117
, a dielectric layer (not shown) and a plate electrode
118
, the storage electrode
116
,
117
having the cylindrical structure. The bit line
111
connects to one of the n-type impurity regions
107
through a bit contact
110
. The word line also serves as the gate electrode
106
. The capacitor connects with the switching transistor through a storage contact
114
and a poly-silicon plug
115
.
As shown in
FIG. 4
, the memory cell includes a p-type silicon substrate
101
, an n-type guard layer
102
surrounding the memory cell, a p-type well
103
surrounded by the n-type guard layer
102
, a field oxide layer
104
to separate memory cells, insulator layers
109
,
112
,
119
, a silicon nitride layer
113
serving as a channel stopper, and a passivation layer
121
.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of forming a semiconductor memory device that can precisely control a formation of rough portions of a capacitor.
According to one aspect of the present invention, for achieving the above object, there is provided a method of forming a semiconductor memory device comprising the steps of: forming a first lower electrode layer having a first rough surface over a semiconductor substrate; forming a second lower electrode layer having a second rough surface over the semiconductor substrate, the second lower electrode layer extending from an end of the first lower electrode layer; forming a dielectric layer over the first and second lower electrode layers; and forming an upper electrode layer over the dielectric layer.
According to another aspect of the present invention, for achieving the above object, there is provided a method of forming a semiconductor memory device comprising the steps of: forming a first lower electrode layer having a first rough surface over a semiconductor substrate; forming a mask layer over the first lower electrode layer, the mask layer having a different etching rate from the first lower electrode layer; patterning the mask layer; forming a second lower electrode layer having a second rough surface over the first lower electrode layer and the mask layer; selectively removing the patterned mask layer and a portion of the second lower electrode located over the patterned mask layer; forming a dielectric layer over the first and second lower electrode layers; and forming an upper electrode layer over the dielectric layer.
According to another aspect of the present invention, for achieving the above object, there is provided a method of forming a semiconductor memory device comprising the steps of: forming a first lower electrode layer having a first rough surface over a semiconductor substrate; forming a first mask layer over the first lower electrode, the first mask layer having a different etching rate from the first lower electrode layer; forming a second mask layer over the first mask layer, the second mask layer having a smaller etching rate from the first mask layer; patterning the first and second mask layers such that a second sidewall of the second patterned mask layer protrudes from a first sidewall of the first patterned mask layer; forming a second lower electrode layer having a second rough surface over the first lower electrode layer and the first and second mask layers; selectively removing the first and second patterned mask layers and a portion of the second lower electrode located over the first and second patterned mask layers; forming a dielectric layer over the first and second lower electrode layers; and forming an upper electrode layer over the dielectric layer.


REFERENCES:
patent: 5366917 (1994-11-01), Watanabe et al.
patent: 5759895 (1998-06-01), Tseng
patent: 5814924 (1998-09-01), Komatsu
patent: 5872041 (1999-02-01), Lee et al.
patent: 5888295 (1999-03-01), Sandhu et al.
patent: 5976931 (1999-11-01), Yew et al.
patent: 4-320370 (1992-11-01), None
patent: 4-368172 (1992-12-01), None

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