Method of forming semiconductor integrated circuit using master

Details Method of forming semiconductor integrated circuit using master Method of forming semiconductor integrated circuit using master

1989-06-15

1992-01-14

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 40, 437 41, 437 51, 437 56, 437 57, 437195, H01L 2170

Patent

active

050810596

ABSTRACT:
A method of forming a semiconductor integrated circuit using a master slice approach includes the steps of: forming a plurality of transistor regions with units of a predetermined number in array on a semiconductor chip; forming a plurality of first wirings extending in parallel at a space therebetween with units of a predetermined length in a discontinuous form so that the first wirings pass through regions corresponding to the transistor regions; forming first contact holes at predetermined positions so that gate regions and source/drain regions of the transistor regions are connected to the first wirings; forming a plurality of second wirings having same forms as the plurality of first wirings so that the second wirings constitute a mesh-like arrangement in combination with the first wirings; and forming second contact holes using a pattern mask programmable in accordance with demanded conditions of a given circuit so that the second contact holes connect the second wirings to the first wirings. By changing only the form of the disposition of the second contact holes, it is possible to simplify an entire process to greatly reduce a turnaround time and make an improvement in yield.

REFERENCES:
patent: 4644382 (1987-02-01), Charransol et al.
patent: 4688070 (1987-08-01), Shiotari et al.
patent: 4750027 (1988-06-01), Asami
patent: 4783692 (1988-11-01), Uratani

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