Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2000-04-14
2001-09-25
Lee, Eddie (Department: 2815)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S127000, C438S612000, C438S613000, C257S782000, C257S783000
Reexamination Certificate
active
06294405
ABSTRACT:
FIELD OF INVENTION
The present invention is drawn to a packaged semiconductor device and method for packaging a semiconductor device. More particularly, the present invention is directed to chip-scale type packages.
BACKGROUND OF THE INVENTION
Chip-scale packages (CSPs) are of current interest in modern semiconductor packaging. The chip-scale package is a relatively new packaging technology, in which a semiconductor die is bonded to a substrate, such as plastic or ceramic, and the substrate is about the same size as the semiconductor die, or more specifically, slightly larger than the semiconductor die. The current focus on chip-scale packages is primarily due to the reduced footprint that such packages provide, which enables the final assembler of an electronic device to improve functionality of the device by incorporating a maximum number of semiconductor devices in a given space.
According to the state of the art, chip-scale packages are relatively costly and have numerous reliability issues, primarily due to the relative complexity of such packages. In addition, the reliability of chip-scale packages, as well as any packaged semiconductor device, is directly proportional to the size of the die. As semiconductor manufacturers incorporate more functionality into a single die, the die size increases absent enabling technology to reduce the feature sizes of the die. As die sizes increase, the reliability of the interconnects between the semiconductor die and the substrate (i.e., first level packaging interconnects) becomes more suspect. In addition, as the size of the packaged semiconductor device increases (thereby increasing footprint size), the reliability of the interconnects between the packaged semiconductor device and the printed circuit board (i.e., second level packaging interconnects) becomes more of a concern. Such reliability problems are primarily due to the differences in thermal expansion coefficients between the materials of the semiconductor die, the substrate, and the printed circuit board, which differences result in stress on the interconnects during changes in ambient temperature and power cycling.
In addition to the issues of decreasing package size and maintaining reliability, there has been an increase in interest in wafer level packaging, that is, packaging semiconductor die in that are in wafer form, before being singulated. It is thought that wafer level packaging may improve reliability and decrease costs by reducing the number of individual components that must be handled by automated machinery. However, a low cost method utilizing conventional packaging technologies to produce a chip-scale package that reliably decouples the thermal expansion mismatch stress between the semiconductor die and the package substrate while assuring BGA (ball grid array) reliability has not yet been developed to enable wafer level packaging.
Accordingly, a need exists in the art for improved chip-scale packages that use standard assembly equipment, are less costly, have high reliability and which may permit wafer level packaging.
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Diaz José R.
Lee Eddie
Motorola Inc.
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