Method of forming self-aligned thin capacitively-coupled...

Details Method of forming self-aligned thin capacitively-coupled... Method of forming self-aligned thin capacitively-coupled...

2002-10-01

2004-07-27

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making regenerative-type switching device

C438S135000

Reexamination Certificate

active

06767770

ABSTRACT:

FIELD OF THE INVENTION
The present invention is directed to semiconductor devices and, more specifically, to semiconductor devices including thyristor-based devices.
BACKGROUND
Recent technological advances in the semiconductor industry have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Presently, single-die microprocessors are being manufactured with many millions of transistors, operating at speeds of hundreds of millions of instructions per second and being packaged in relatively small, air-cooled semiconductor device packages. The improvements in such devices have led to a dramatic increase in their use in a variety of applications. As the use of these devices has become more prevalent, the demand for reliable and affordable semiconductor devices has also increased. Accordingly, the need to manufacture such devices in an efficient and reliable manner has become increasingly important.
An important part in the circuit design, construction, and manufacture of semiconductor devices concerns semiconductor memories and other circuitry used to store information. Conventional random access memory devices include a variety of circuits, such as SRAM and DRAM circuits. The construction and formation of such memory circuitry typically involves forming at least one storage element and circuitry designed to access the stored information.
There are a number of semiconductor memories in widespread use. Two such semiconductor memories are SRAM and DRAM. DRAM is very common due to its high density (e.g., high density has benefits including low price). DRAM cell size is typically between 6 F
2
and 8 F
2
, where F is the minimum feature size. However, with typical DRAM access times being about 50 nSec, DRAM is relatively slow compared to typical microprocessor speeds and requires refresh. SRAM is another common semiconductor memory that is much faster than DRAM and, in some instances, is an order of magnitude faster than DRAM. Also, unlike DRAM, SRAM does not require refresh. SRAM cells are typically made using 4 transistors and 2 resistors or 6 transistors, which result in much lower density and is typically between about 60 F
2
and 100 F
2
.
Various SRAM cell designs based on NDR (Negative Differential Resistance) constructions have been introduced, ranging from a simple bipolar transistor to complicated quantum-effect devices. These cell designs usually consist of at least two active elements, including an NDR device. In view of size considerations, the construction of the NDR device is important to the overall performance of this type of SRAM cell. One advantage of the NDR-based cell is the potential of having a cell area smaller than four-transistor and six-transistor SRAM cells because of the smaller number of active devices and interconnections.
Conventional NDR-based SRAM cells, however, have many problems that have prohibited their use in commercial SRAM products. These problems include, among others: high standby power consumption due to the large current needed in one or both of the stable states of the cell; excessively high or excessively low voltage levels needed for the cell operation; stable states that are too sensitive to manufacturing variations and provide poor noise-margins; limitations in access speed due to slow switching from one state to the other; limitations in operability due to temperature, noise, voltage and/or light stability; and manufacturability and yield issues due to complicated fabrication processing.
A thin capacitively-coupled thyristor-type NDR device can be effective in overcoming many previously unresolved problems for memory applications. An important consideration in the design of the thin capacitively-coupled thyristor involves designing the body of the thyristor sufficiently thin, so that the capacitive coupling between the control port and the thyristor base region can substantially modulate the potential of the base region. For memory-cell applications, another important consideration in semiconductor device design, including those employing thin capacitively-coupled thyristor-type devices, includes forming devices in a very dense array.
NDR devices including thyristors are also widely used in power switching applications because the current densities carried by such devices can be very high in their on state. In typical power applications, high voltages force thyristor devices to be very large. In some cases, the entire wafer is used to make one thyristor (e.g., no logic devices are combined with the thyristor). The performance of such NDR devices is dependent on many physical parameters, including the length of various regions of the thyristor. One manner for forming regions to a selected length includes using a masking technique such as photolithography. On very large thyristors, diffusion and/or epitaxial grown layer(s) may also be used. However, variation in the photolithographic process provided by currently-available photolithography techniques can hinder the ability to make one or more of the regions to a desired length and/or width, which can cause problems in some applications.
In high-density memory applications where high temperature diffusion steps can degrade logic devices and where photolithography is being used to produce the smallest features possible, traditional techniques used for fabricating thyristors, including those discussed above, do not work well. Specifically, additional length may be necessary for misalignment and process variation, which makes the device larger. The larger device may be acceptable for power thyristors, but not necessarily for devices such as high density memory cells. In addition, if a salicide block is also needed to prevent a salicide short between the regions of the thyristor, the length of the region being defined can be even longer (e.g., if the salicide block is also defined by photolithography, requiring additional space for misalignment). In a memory cell having mirrored thin capacitively-coupled thyristor elements, width variation aggravates the performance of the cell because misalignment can cause adjacent cells to have regions of different widths.
These and other design considerations have presented challenges to efforts to implement such a thin capacitively-coupled thyristor in bulk substrate applications, and in particular to highly dense applications.
SUMMARY
The present invention is directed to the manufacture of a thyristor in a manner that addresses the above-mentioned challenges. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a gate and a spacer are used to mask portions of a semiconductor substrate for implanting the substrate with a dopant for forming a thyristor. A portion of the substrate is doped, and a thyristor gate is formed over a first region of the doped substrate. The gate is used to mask the first region and a second region of the substrate is doped. A sidewall spacer is formed adjacent to the gate over the second region and used to mask the second region while a third region of the substrate is doped. In the resulting structure, the first and third regions are each contiguously adjacent to the second region. The thyristor includes doped regions of which the first and second regions are base regions and the third region is an emitter region of the thyristor. The dimension of the second doped thyristor region is controlled using a spacer for self-alignment. If left in place, the sidewall spacer also acts to block the formation of self-aligned silicide (salicide) on the surface of the second doped thyristor region. In this manner, the alignment and definition of the second doped portion is facilitated.
In a related embodiment, a thyristor includes a capacitively-coupled control port and an underlying thyristor-body region being aligned so that the control port does not extend beyond one or both of the junction-defining edges.
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