Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Using epitaxial lateral overgrowth
Reexamination Certificate
2002-04-09
2004-07-27
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Using epitaxial lateral overgrowth
C438S349000, C438S350000, C438S357000, C438S363000, C438S592000
Reexamination Certificate
active
06767798
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor processing, and in particular, to a method of forming a self-aligned bipolar transistor with a raised extrinsic base.
BACKGROUND OF THE INVENTION
Processes are known for fabrication of bipolar transistors having an extrinsic base region self-aligned to the sacrificial emitter structure. One example of such a process is described by M. Racanelli et al. in an article entitled “Ultra High Speed SiGe NPN for Advanced BiCMOS Technology”, in the IEDM-2001 proceedings. Link base and extrinsic base implants are blocked from penetration in the intrinsic device area by the sacrificial emitter feature and the sacrificial emitter feature with a side wall spacer, respectively. Heavy p-type implants required to convert epitaxially deposited base material into a low resistivity extrinsic base region result in the generation of interstitial defects in the single crystal portion of the extrinsic base. The presence of interstitial defects promotes the transient enhanced diffusion of boron from the extrinsic base region into the intrinsic base during subsequent thermal processing. Interstitial defects also promote transient diffusion of the boron incorporated in the epitaxial base layer which leads to the effective base widening and the device speed reduction.
Another problem associated with the fabrication of higher speed bipolar transistors is the need to form thinner base films, which directly translates into a high base resistance.
FIG. 1
illustrates a cross-sectional view of a typical npn bipolar transistor. The extrinsic link base region (R
bshl
) comprises a thin Si, SiGe or SiGe:C epitaxial layer as used in the intrinsic base. Although heavily doped, this region will have higher resistance for thinner base films (faster transistors).
The graph shown above illustrates the calculated dependence of base resistance R
b
on the link base sheet resistance (R
bshl
) for a given device geometry. A factor of three redution in the link base resistance (R
bshl
) will result in a significant (approximately 80 ohm) reduction in base resistance (R
b
).
In view of the above, it is apparent that there is a need to provide a high speed bipolar transistor and a method of fabricating a high speed bipolar transistor which reduces or avoids the above mentioned problems.
SUMMARY OF THE INVENTION
In accordance with the invention, a new and improved bipolar transistor and a method of forming same is provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase in thickness of the extrinsic base provides a less resistive layer of the heavily doped link base region.
The method of forming the bipolar transistor includes depositing a first epitaxial layer on a substrate to form a base region having an intrinsic base region and an extrinsic base region. The extrinsic base region is raised by depositing a second epitaxial layer over a portion of the first epitaxial layer such that the thickness of the extrinsic base layer is x and the thickness of the intrinsic layer is y, wherein x>y.
The second epitaxial layer is deposited using a chemical vapor epitaxial device where heavily p-type (e.g. boron) doped silicon is deposited selectively on exposed silcon surfaces. In order to improve process selectivity, a heavily p-type doped SiGe may be optionally deposited, where the concentration of Ge to Si is gradually reduced from above 5% to close to 0% during the epitaxy process. As such, the second epitaxy layer has the highest concentration of Ge near the interface of the first epitaxy layer and the second epitaxy layer. The concentration of Ge is gradually reduced to near 0% at the top surface of the second epitaxy region.
Other aspects, features and techniques of the invention will become apparent to one skilled in the relevant art in view of the following detailed description of the invention.
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Kalnitsky Alexander
Park Sang H.
Rowlandson Michael
Scheer Robert F.
Shatalov Alexei
Blakely , Sokoloff, Taylor & Zafman LLP
Brewster William M.
Coleman W. David
Maxim Integrated Products Inc.
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