Method of forming self-aligned bipolar transistor

Details Method of forming self-aligned bipolar transistor Method of forming self-aligned bipolar transistor

2002-11-20

2004-02-03

Thomas, Tom (Department: 2811)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Walled emitter

C438S348000, C438S235000, C438S339000, C438S364000, C438S369000, C438S309000, C438S691000

Reexamination Certificate

active

06686250

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to semiconductor processing, and in particular, to a method of forming a self-aligned bipolar transistor.
BACKGROUND OF THE INVENTION
Processes are known for fabrication of bipolar transistors having a self-aligned structure, using a first polysilicon layer for the extrinsic base contact and a second polysilicon layer for the emitter contact, for example, as described in an article entitled “High Speed Polysilicon Emitter Base Bipolar Transistor” by Hee K. Park et al., IEEE Electron Device Letters, EDL-7 no. 12 (December 1986). Self-alignment of the base and the emitter allows for minimization of both the extrinsic base resistance and the collector-base junction capacitance.
Another example of a double polysilicon structure is described in an article by Warnock et al. entitled “50 GHz Self-Aligned Silicon Bipolar Transistors with Ion Implanted Base Profiles”, IEEE Electron Device Letters, Vol. 11, no. 10 (October 1990).
The conventional double-poly process requires a first and second polysilicon layer, and the resulting structure has a highly non-planar topography. In particular, the topography of the polysilicon layer forming the emitter may have a sharp discontinuity in the emitter region, requiring a relatively thick polysilicon layer to fill the emitter gap without voids. The latter complicates subsequent processing steps such as metallization and dielectric planarization and creates problems associated with contact imaging and contact etching. The depth differential of the contact to the emitter and the contact to the sinker is relatively large and the aforementioned are in close proximity to one another. The resulting high aspect ratio contact holes are difficult to form while preserving the underlying salicide. As such, the emitter-base junction may be damaged during etching of the emitter opening in the first polysilicon layer because there is no etch stop due to little or no etch selectivity to the underlying silicon. Damage to the emitter-base junction due to over etching may have a severe impact on the noise of the transistor for analog applications. Variable recessing of the base during silicon over etch and consequent sidewall spacer width variability may lead to variability in emitter width. The ensuing variations in emitter-base capacitance along the sidewall spacer edge and emitter polysilicon contact area may not be avoided without exacerbating the topography related problems. Furthermore, doping in the link region of the base can not be controlled independently of the base implant, leading to a higher than desirable base resistance and/or emitter-base edge leakage problems.
The latter process for a double-poly self-aligned npn bipolar transistor is complex and suffers from a number of process related problems, which lead to reliability issues in the resulting device structure.
As described in an article entitled “A High Speed Bipolar Technology Featuring Self-Aligned Single Poly Base and Submicrometer Emitter Contacts” by W. M. Huang et al. IEEE Electron Devices Letters vol. 11, no. 9 (September 1990), problems associated with etching double polysilicon structures may be avoided by fabricating the emitter contact with the first layer of polysilicon. The latter process is known as self-aligned trench isolated polysilicon electrodes (STRIPE) process. The polysilicon layer is etched to define trenches for isolating the emitter region from the base regions. A low energy boron implant into the trench region defines a link region. The trench is then filled with oxide and the emitter region is n+doped by an arsenic implant. This process reduces the possibility of etch damage of the active emitter area and avoids the highly non-planar topography of the conventional double poly process. Other process related problems remain in the polysilicon electrodes however, and additional processing steps are needed, such as etching of the polysilicon layer to form narrow trenches for isolation between the emitter and base regions.
Another approach to forming a single polysilicon self-aligned bipolar transistor, known as the ASPECT process, comprises forming a p type base region in the device well as described above, and then forming an emitter structure by depositing a layer of polysilicon, patterning and etching the polysilicon to leave an emitter structure in the form of a mesa. The emitter mesa is isolated with oxide sidewall spacers before contacts are formed to the base contact region surrounding the emitter mesa. The latter process however, does not avoid the risk of damage to the underlying silicon layer in the base contact region during the overetch of the polysilicon layer region.
In view of the above, it is apparent that there is a need to provide a bipolar transistor and a method of fabricating a bipolar transistor which reduces or avoids the above mentioned problems.
SUMMARY OF THE INVENTION
In accordance with the invention, a new and improved bipolar transistor is provided in which a sacrificial emitter stack is not required to mask link base implants from penetrating into the intrinsic device area. The bipolar transistor is fabricated in accordance with a less complicated scheme in which the emitter polysilicon stack (in contact with the base) of arbitrary dimensions serves as a mask for self-aligned (to the emitter) extrinsic base implants. The emitter polysilicon stack includes a plug structure, which is self-aligned to the emitter polysilicon feature, to block heavy p+ implants from penetrating into the n+ emitter polysilicon. The emitter polysilicon stack is also encapsulated with an oxide for protection against chemicals typically employed to subsequently remove the silicon nitride plug.
The method of forming the bipolar transistor includes forming an emitter stack on a substrate. The emitter stack comprises a first polysilicon emitter structure and a plug structure. The emitter stack defines the substrate into a masked portion and exposed adjacent portions. The exposed adjacent portions are selectively doped with a dopant to define an extrinsic base region, wherein the dopant is blocked from entering the masked portion. After selectively doping the extrinsic base region, the plug structure is removed from the emitter stack and a second polysilicon or refractory metal silicide (e.g. WSi
2
) emitter structure is formed on the first polysilicon emitter structure to define the emitter region of the bipolar transistor. The emitter region is characterized by a y-shaped structure formed from the bilayer polysilicon emitter structures.
Other aspects, features and techniques of the invention will become apparent to one skilled in the relevant art in view of the following detailed description of the invention.


REFERENCES:
patent: 5818153 (1998-10-01), Allen
patent: 5882976 (1999-03-01), Blair
patent: 6051873 (2000-04-01), Yoshihisa
patent: 6194280 (2001-02-01), Johnson
patent: 6248650 (2001-06-01), Johnson
patent: 6384469 (2002-05-01), Chantre

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