Method of forming polycide

Details Method of forming polycide Method of forming polycide

2000-03-09

2001-01-23

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

C438S592000

Reexamination Certificate

active

06177335

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming polycide. More particularly, the present invention relates to a method of forming polycide in a semiconductor device.
2. Discussion of Related Art
As a semiconductor device requires higher density of integration, the impurity region and gate width are reduced in size. Unfortunately, operation speed of the semiconductor device is decreased due to both the increased contact resistance of the impurity region and the increased sheet resistance of the gate.
To counteract these effects, the resistance is reduced by forming wires in a semiconductor device from a low resistance substance such as an Al alloy, W and the like and/or by forming a silicide layer on a polysilicon layer on the gate electrode. When the silicide layer is formed on the gate of polysilicon, sheet resistance is also reduced by forming a silicide layer on the surface of the impurity region.
As mentioned in the above description, the major factor lowering the operation speed of a semiconductor device is the high resistance at the gate due to the strict design rules of the semiconductor device. Therefore, it is essential to fabricate a gate electrode of low resistance to improve the operation speed of the device. For this purpose, the gate electrode has a refractory metal silicide of low specific resistance positioned thereon. A gate electrode having such a configuration is called a polycide(silicide on doped polycrystalline silicon) type gate electrode. WSi
2
prevails in forming the polycide structure. Yet, the formation of a silicide with a resistance lower than that of WSi
2
is required as the area occupied by a unit device decreases due to the high density of a device. In this case, the specific resistance of WSi
2
ranges from 60 to 200 &mgr;-cm. CoSi
2
and TiSi
2
, where the specific resistance ranges from 15 to 20 &mgr;-cm , are the most promising substitute materials.
Various methods of forming a polycide are represented by the two following procedures.
In the first procedure a silicide is formed by depositing a metal layer on a doped polysilicon layer and by reacting the metal with the silicon through thermal treatment. Unfortunately, the silicide of metal-Si lacks uniformity and sufficient thickness.
Generally, a pure metal reacts vigorously with silicon, making the interface between the Si and the silicide rough such that it becomes difficult to pattern a gate electrode. This is explained in detail in J.S. Byun et al., J. Electrochem. Soc., vol. 144,3175 (19997). Moreover, it is difficult to form a uniform silicide due to the high density of dopants as the metal reacts with the heavily-doped polysilicon.
In the second procedure, a silicide is directly deposited on a doped polysilicon layer instead of using the above-described thermal process. Generally, a silicide layer is formed on a doped polysilicon layer by sputtering from a silicide composite target. However, this method generates particles on the forming silicide. Also, it is difficult to form a silicide of uniform composition due to the different sputtering ratios of respective components in the metal/silicon composite target hence particles are generated.
Additionally, when a high performance dual gate CMOS device is fabricated by the above two methods, it is difficult to carry out a doping process for a PMOS device where boron is used as a dopant. This is because boron has a very high diffusivity and can diffuse into a polysilicon layer of relatively low thickness, into a gate insulating layer, and a silicon substrate. Thus, the reliance of a device is decreased.
FIG. 1A
to
FIG. 1C
show cross-sectional views of a method for forming polycide in a semiconductor device according to the related art. Referring to
FIG. 1A
, an active region and a device-insulation region are defined by forming a field oxide layer in a predetermined portion of the silicon substrate
10
by LOCOS(Local Oxidation of Silicon) or the like. A gate oxide layer
11
, as a gate insulating layer, is formed by thermal oxidation on a surface of the silicon substrate
10
.
A doped polysilicon layer
120
, doped with impurities(in-situ doped polycrystalline silicon) to form a gate electrode, is deposited on the gate oxide layer
11
by chemical vapor deposition(hereinafter abbreviated CVD). Alternately, an undoped polysilicon layer
120
, having been deposited by CVD, is doped by ion-implantation. The lower structure of the gate electrode is formed by patterning the polysilicon layer
120
. In this case, considering the total height of a gate electrode, the polysilicon layer
120
is formed to the thickness which does not include the thickness of a silicide layer to be formed. Therefore, the thickness of the polysilicon layer
120
is reduced by the thickness of the suicide layer. When a dual gate CMOS device is fabricated, the doping step for a PMOS device becomes very difficult when boron is used as the dopant. This is because boron has a very high diffusivity and diffuses into a polysilicon layer of low relative thickness and diffuses into the gate insulating layer and silicon substrate.
Referring to
FIG. 1B
, a metal layer is formed by depositing Co or Ti as a metal for forming a silicide on the polysilicon layer
120
by sputtering. In this case, to be proper for the design rule of a gate electrode, the thickness of the metal layer depends on the total thickness which includes the thickness of the polysilicon layer
120
. A silicide layer
130
is formed by reacting metal with silicon by carrying out a rapid thermal annealing(hereinafter abbreviated RTA) on the polysilicon and metal layers. Instead of forming the silicide layer
130
by RTA, a silicide layer
130
may be formed by depositing silicide directly on the doped polysilicon layer
120
by using a silicide composite target. Referring to
FIG. 1C
, after the silicide layer
130
has been coated with photoresist, a photoresist pattern(not shown in the drawing) is formed by exposure and development of the photoresist using a mask for defining a gate electrode. A final gate electrode
131
and
121
, comprised of a remaining silicide layer
131
and a remaining doped polysilicon layer
121
, is formed by removing the silicide layer and the polysilicon layer which are not covered with the photoresist pattern. In this case, the final gate electrode
131
and
121
is formed by carrying out dry etching on the silicide layer and the doped silicon layer using the photoresist pattern as a mask. Then, the photoresist pattern is removed by O
2
ashing.
Though not shown in the drawing, semiconductor devices such as a transistors and the like are completed by forming a lightly doped drain(hereinafter abbreviated LDD) region in a predetermined portion of the substrate, by forming a gate sidewall spacer and by forming a source and a drain and the like. Unfortunately, the above method of forming polycide according to the related art by forming silicide from the reaction of metal/silicon by RTA has difficulty in forming a silicide layer having uniformity and sufficient thickness due to the high density of dopants, wherein the metal reacts with the heavily-doped polysilicon. When a silicide is directly deposited onto a doped polysilicon layer instead of using a thermal process, this method of the related art generates particles on the forming silicide. Accordingly, it is difficult to form a silicide of uniform composition due to the different sputtering ratios of respective components in the metal/silicon composite target, which results in the generation of particles. Moreover, when a dual gate CMOS device is fabricated for high performance by the above two methods, it is difficult to carry out a doping process for a PMOS device using boron as a dopant. This is because boron has a very high diffusivity and diffuses into a polysilicon layer of low relative thickness, and diffuses into the gate insulating layer and the silicon substrate. Thus, reliability of the device is decreased.
SUMMARY OF THE INVENTION
Accordingly, the p

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