Method of forming multiple gate oxide thicknesses on a wafer sub

Details Method of forming multiple gate oxide thicknesses on a wafer sub Method of forming multiple gate oxide thicknesses on a wafer sub

1995-11-21

1997-09-30

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 43, 148DIG116, 148DIG163, H01L 21266

Patent

active

056725213

ABSTRACT:
An integrated circuit device and manufacturing process wherein a first region is formed in a substrate with a dopant that enhances oxide formation and a second region is formed in the substrate with a dose of nitrogen that retards oxide formation. An oxide layer is grown over the first and the second regions and over a third region of the substrate such that the first, second, and third regions yield differing thicknesses of the oxide layer.

REFERENCES:
patent: 4651406 (1987-03-01), Shimizu et al.
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patent: 5330920 (1994-07-01), Soleimani et al.
patent: 5432114 (1995-07-01), O
patent: 5532181 (1996-07-01), Takebuchi et al.

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