Method of forming multilayered wiring structure of semiconductor

Details Method of forming multilayered wiring structure of semiconductor Method of forming multilayered wiring structure of semiconductor

1993-03-15

1993-11-02

Quach, T. N.

Fishing, trapping, and vermin destroying

437228, 437246, 437189, H01L 21461

Patent

active

052583287

ABSTRACT:
A conductive film is formed on first and second prospective lower wiring layer formation regions on a semiconductor substrate and a prospective isolation region between the lower wiring layers. An insulating interlayer is formed on the semiconductor substrate including this conductive film and is partially removed to obtain an opening in which the conductive film is exposed. In addition, an upper wiring layer is formed on the upper surface of the semiconductor substrate. The conductive film and an upper wiring portion located on the conductive film are simultaneously and selectively removed to obtain isolated upper layer portions and isolated conductive film portions. Alternatively, two wiring portions each having at least two lower wiring portions electrically insulated from each other and adjacent to each other are formed on a semiconductor substrate having a stepped portion, and an insulating interlayer is formed thereon. The insulating interlayer is removed until the first and second wiring portions are exposed. In addition, the stepped portion formed in the second wiring portion is buried with a third insulating film. A method of forming a highly reliable multilayered wiring structure at a high yield can be obtained.

REFERENCES:
patent: 4758306 (1988-07-01), Cronin et al.
patent: 4876212 (1989-10-01), Koury
patent: 5169802 (1992-12-01), Yeh
patent: 5189506 (1993-02-01), Cronin et al.

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