Method of forming MOS-gated semiconductor devices having mesh ge

Details Method of forming MOS-gated semiconductor devices having mesh ge Method of forming MOS-gated semiconductor devices having mesh ge

1995-01-04

1995-11-21

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 48, 437 56, 148DIG126, H01L 2177

Patent

active

054686687

ABSTRACT:
A pattern for a wafer for a MOS-gated semiconductor device includes plural ribbons extending from a source contact region to another source contact region, each of the ribbons having a single source region between two channel regions, so as to increase the device's current-carrying capability per unit area relative to the prior art. The pattern increases the size of the active current-carrying area (the channel and neck regions of the device) relative to the area of the source contact areas. The source contact regions may be discrete or linear, and the ribbons may extend therefrom perpendicularly or at other angles.

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patent: 4561003 (1985-12-01), Tihanyi et al.
patent: 4644637 (1987-02-01), Temple
patent: 4677452 (1987-06-01), Zommer
patent: 4833513 (1989-05-01), Sasaki
patent: 5262339 (1993-11-01), Mori et al.
patent: 5288653 (1994-02-01), Enjoh
patent: 5395776 (1995-03-01), Shibib

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