Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Reexamination Certificate
1999-01-11
2001-01-23
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
Reexamination Certificate
active
06177297
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of forming a metallic fuse. More particularly, the present invention relates to a method of forming a metallic fuse that demands a lower laser power for circuit repair.
2. Description of Related Art
In the manufacturing of semiconductor memories, product yield is of great importance. If there is one or more defective memory cells in a semiconductor memory product, the finished product as a whole is defective and has to be scrapped or repaired. As the level of device integration increases. the number of defective memory cells also increases proportionately. In other words, as the level of integration of semiconductor memory devices increases, product yield is correspondingly lowered.
As advanced techniques for fabricating semiconductor memory devices develop, the packing density of memory devices increases considerably. Consequently, fabrication becomes increasingly difficult and complex. Since impure particles (or fragments) appear when the memory devices are produced, a lower yield rate for highly integrated circuits is unavoidable. Hence, to increase the yield rate of circuit fabrication, redundant backup devices are often added to boost the product yield of conventional operations. Besides memory cell array for storing binary bits, an additional backup memory cell array is often provided so that defective memory cells can be easily replaced. Each redundant memory cell is connected to a word line and a bit line, respectively. Thus, even if more than a thousand defective memory cells are found after inspection, the defective memory cells can be replaced by the redundant memory cells in the backup array. Consequently, a defect-free memory array can be obtained on a silicon chip.
The above scheme of using redundant elements in memory circuits has the advantages of a higher yield and defect-free circuits. However, in exceptional cases, when the number of defective elements is higher than the number of redundant elements provided, even this scheme does not work.
In general, the above scheme is implemented by forming a redundant memory cell array around a main memory cell array when the semiconductor memory devices are manufactured. The main memory cell array and the redundant memory cell array are normally linked by polysilicon fuses, which can be melted away by a laser beam or a high current. When a defective memory cell needs to be fixed, the protective fuse is broken by a laser beam or an electric current. On the other hand, if the defective cell does not require fixing. the protective fuse can stay as it is.
FIGS. 1A and 1B
are schematic, cross-sectional views showing the progression of manufacturing steps in forming a conventional polysilicon fuse.
First, as shown in
FIG. 1A
, a local oxidation of silicon (LOCOS) method is used to form a field oxide layer
12
over a semiconductor substrate
10
. Then, the field oxide layer
12
is patterned to form an active region
13
. Next, a polysilicon fuse structure
14
is formed above the field oxide layer
12
. Thereafter, an inter-metal dielectric layer
16
is formed covering the entire substrate structure. including the polysilicon fuse
14
. Subsequently, photolithographic and etching techniques are used to form an opening
17
in the inter-metal dielectric layer
16
that exposes a portion of the active region
13
. Next, a conductive plug
18
is formed inside the opening
17
, and then a layer of conductive material is deposited over the inter-metal dielectric layer
16
and makes electrical contact with the conductive plug
18
. The conductive material is patterned to form a conductive layer
20
.
Similarly, using the above method, another inter-metal dielectric layer
22
is formed over the conductive layer
20
. Next, photolithographic and etching operations are again used to form another opening
24
in the inter-metal dielectric layer
22
and expose a portion of the conductive layer
20
. Thereafter, another conductive plug
26
is formed inside the opening
24
, and then a conductive material is formed over the inter-metal dielectric layer
22
and makes electrical contact with the conductive plug
26
. The conductive material is patterned to form a conductive layer
28
.
Next, a chemical-vapor deposition method is used to form a silicon nitride layer over the entire substratte structure that includes the conductive layer
28
. The silicon nitride layer
30
serves as a protective layer in subsequent operations. Thereafter, conventional photolithographic and etching methods are used to pattern the silicon nitride layer
30
so that an opening
32
is formed in the silicon nitride layer
30
. The opening
32
exposes a portion of the inter-metal dielectric layer
22
. Moreover, the opening
32
is formed in a location vertically above the polysilicon fuse structure
14
.
Next, as shown in
FIG. 1B
, when a defective memory cell needs to be reinstated, the polysilicon fuse
14
of that particular cell has to be cut by a laser beam. Consequently, the defective memory cell is replaced by a redundant memory cell. In the laser cutting operation, the laser beam penetrates the opening
32
and passes through the inter-metal dielectric layers
16
and
22
to reach the polysilicon fuse
14
, deep below, hence cutting open the luse connection and achieving the necessary defective cell replacement. Since the laser beam's power is very high, portions of the inter-metal dielectric layers
16
and
22
penetrated by the laser beam sublimate and turn into gas. Ultimately, a deep opening
34
that exposes the field oxide layer
12
is be formed when the memory cell restoration is completed.
However, in the conventional method of fabricating polysilicon fuses, the fuses are still laid on top of the field oxide layer even though there are more than three intervening inter-metal dielectric layers. Since the polysilicon fuses are too deep below the surface, the laser beam's power must be very high in order for it to carry out the reparation. Furthermore, when the polysilicon fuses are too deep within the structure, it is difficult for the laser beam to reach the fuse without part of the laser beam being dispersed. Hence. much laser power is wasted and yield of the reparation is low.
In practice, when the laser power used in burning a polysilicon fuse is between 2×10
−6
to 3×10
−6
joules/sec, the rate of repair is 50% at most. If a higher rate of repair is desired, the laser power output has to be increased to an even higher value. However, turning up the laser power can easily damage part of the silicon wafer.
In light of the foregoing, there is a need to provide a method of forming a polysilicon fuse that requires less laser power to achieve the desired result.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method of forming a metallic fuse capable of lowering the laser power necessary for performing a memory cell replacement operation.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a metallic fuse that permits use of a less powerful laser for memory cell repair. The method comprises the steps of providing a substrate having a field oxide layer that defines an active region already formed thereon. Then, a first conductive layer and a metallic fuse are formed over the substrate, wherein the first conductive layer is electrically coupled to the active region. Next, a dielectric layer is formed over the first conductive layer and the metallic fuse. Thereafter, a second conductive layer is formed above the dielectric layer. Subsequently, a protective layer having an opening is formed over the second conductive layer and the dielectric layer. The opening is positioned vertically above the metallic fuse. Finally, the metallic fuse is burned by a laser beam to open the electrical connection when a memory cell repair is necessary.
One aspect of this invention is the
Chen Jacob
Lin Wen-Jeng
Bowers Charles
Christianson Keith
United Microelectronics Corp.
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