Method of forming metal-strapped polysilicon gate electrode for

Details Method of forming metal-strapped polysilicon gate electrode for Method of forming metal-strapped polysilicon gate electrode for

1987-08-13

1988-07-05

Ozaki, George T.

Fishing, trapping, and vermin destroying

437 34, 437 57, 437200, 437913, H01L 21425

Patent

active

047554789

ABSTRACT:
A process for forming a planarized, low sheet resistance FET. A gate stack is defined on an exposed surface of a semiconductor substrate, the gate stack including a gate mask disposed on a patterned polysilicon layer. First and second diffusion having first and second silicide electrodes are then formed on the substrate, to provide low sheet resistance source and drain electrodes. An insulating layer is then formed on the substrate, and is planarized to expose an upper surface of the gate mask. The gate mask is then removed in wet H.sub.3 PO.sub.4 to define an aperture in the insulating layer that exposes the polysilicon layer, and a conductive material is selectively grown on the substrate to provide a metal-strapped polysilicon gate electrode that is relatively co-planar with the planarized insulating layer.

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