Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2008-11-18
2010-10-19
Ghyka, Alexander G (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S741000, C257SE23069, C438S612000
Reexamination Certificate
active
07816787
ABSTRACT:
Techniques for manufacturing a bond pad structure are provide. A method includes providing a substrate. A metal pad and passivation layer are formed over the substrate. The passivation layer includes an opening to expose a portion of the metal pad. A first film is deposited at least over the exposed portion of the metal pad. A second film is deposited over the first film. A photoresist layer is deposited over the substrate, and a trench is formed in the photoresist layer directly over the portion of the metal pad. A first layer is electroplated in the trench over the second film, and a barrier layer is electroplated in trench over the first layer. A termination electrode, comprising tin, is electroplated in the trench over the barrier layer. The photoresist layer is removed. In addition, the method can include etching to remove the second film and first film beyond a predetermined area. The termination electrode is then reflowed. The barrier layer prevents formation of an intermetallic compound in proximity to the first layer by precluding diffusion of tin from the termination electrode to the first layer. In a specific embodiment, the first layer includes stress release copper underneath a barrier layer which includes nickel.
REFERENCES:
patent: 3663184 (1972-05-01), Wood et al.
patent: 4290079 (1981-09-01), Carpenter et al.
patent: 4514751 (1985-04-01), Bhattacharya
patent: 5937320 (1999-08-01), Andricacos et al.
patent: 6316813 (2001-11-01), Ohmi et al.
patent: 6417089 (2002-07-01), Kim et al.
patent: 6452270 (2002-09-01), Huang
patent: 6586303 (2003-07-01), Wu
patent: 6740427 (2004-05-01), Datta et al.
patent: 6798050 (2004-09-01), Homma et al.
patent: 7176583 (2007-02-01), Daubenspeck et al.
patent: 7462556 (2008-12-01), Wang
patent: 2002/0185733 (2002-12-01), Chow et al.
patent: 2004/0183195 (2004-09-01), Huang et al.
Requirement for Restriction/Election for U.S. Appl. No. 11/176,871, mailed on May 14, 2007, 6 pages.
Non-Final Office Action for U.S. Appl. No. 11/176,871, mailed on Jun. 29, 2007, 13 pages.
Final Office Action for U.S. Appl. No. 11/176,871, mailed on Feb. 28, 2008, 15 pages.
Advisory Action for U.S. Appl. No. 11/176,871, mailed on Jun. 16, 2008, 3 pages.
Notice of Allowance for U.S. Appl. No. 11/176,871, mailed on Jul. 30, 2008, 9 pages.
Chan, K.C., “Investigation of Cr/Cu/CuNi Under Bump Metallization for Lead-Free Applications,” Electronics Packaging Technology Conference 2002, IEEE Explore, vol. 4, pp. 270-275.
Ghyka Alexander G
Nikmanesh Seahvosh J
Semiconductor Manufacturing International (Shanghai) Corporation
Townsend and Townsend / and Crew LLP
LandOfFree
Method of forming low stress multi-layer metallurgical... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming low stress multi-layer metallurgical..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming low stress multi-layer metallurgical... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4203380