Method of forming isolation regions in a MOS transistor device

Details Method of forming isolation regions in a MOS transistor device Method of forming isolation regions in a MOS transistor device

1996-02-26

1997-10-07

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 26, 437 56, H01L 21336, H01L 218238

Patent

active

056747608

ABSTRACT:
The present invention is directed to a MOS transistor and its method of fabrication. The transistor includes isolating layers below source/drain regions of the transistor. In this manner, lateral diffusion occurring in the source/drain regions can be retarded. Accordingly, the fabricated. MOS transistor has the advantages of shallow junction depth, low junction capacitance, and better punchthrough resistance. Furthermore, since the bulk of the MOS transistor might be connected to a constant voltage, most likely ground, via a contact region, the floating body effects typically encountered in SOI (silicon-on-insulator) devices can be avoided.

REFERENCES:
patent: 4700454 (1987-10-01), Baerg et al.

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