Method of forming isolation layer of semiconductor memory...

Details Method of forming isolation layer of semiconductor memory... Method of forming isolation layer of semiconductor memory...

2008-06-27

2009-11-03

Blum, David S (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C257SE21002

Reexamination Certificate

active

07611964

ABSTRACT:
The present invention relates to a method of forming an isolation layer of a semiconductor memory device. According to a method of fabricating a semiconductor memory device in accordance with an aspect of the present invention, a tunnel insulating layer and a charge trap layer are formed over a semiconductor substrate. An isolation trench is formed by etching the charge trap layer and the tunnel insulating layer. A passivation layer is formed on the entire surface including the isolation trench. A first insulating layer is formed at a bottom of the isolation trench. Portions of the passivation layer, which are oxidized in the formation process of the first insulating layer, are removed. A second insulating layer is formed on the entire surface including the first insulating layer.

REFERENCES:
patent: 7364975 (2008-04-01), Culmsee et al.
patent: 2006/0223321 (2006-10-01), Nam et al.
patent: 2007/0243693 (2007-10-01), Nemani et al.
patent: 2009/0035915 (2009-02-01), Su

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