Method of forming isolation

Details Method of forming isolation Method of forming isolation

1994-08-18

1995-12-05

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 69, H01L 2176

Patent

active

054729068

ABSTRACT:
A first underlaid oxide layer, a polysilicon layer, and a first silicon nitride layer are formed on a silicon substrate in this order. Using a photoresist as a mask, a portion of the first silicon nitride layer, the polysilicon layer, the first underlaid oxide layer and the silicon substrate which is to be an isolation region is etched by a depth which regulates a length of bird's beak and a threshold voltage drop of a FET adequately. After forming a second underlaid oxide layer and a second silicon nitride layer, silicon nitride side walls of more than 25 nm in thickness are formed. An isolation oxide layer is formed by selective oxidation, using the silicon nitride layer as a mask. Favorable etched depth in the step of removing the silicon substrate is one third of the thickness of the isolation oxide layer. Favorable etched depth in case of a normal FET is 20-100 nm. Thus, bird's beak length is reduced, while adequately maintaining the threshold of the transistor at formation of the isolation of transistor. In a DRAM cell pattern, isolation of not exceeding 0.2 .mu.m width can be formed.

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