Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1997-07-07
1999-11-09
Fourson, George
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438427, 438951, 438704, 438732, H01L 21762
Patent
active
059813555
ABSTRACT:
A method of forming an isolating region of a semiconductor device including the steps of: forming first insulating layers which vary in width on a substrate; forming trenches which vary in width on the substrate by using the first insulating layers as a mask; forming second insulating layers on the trenches and the first insulating layers; exposing the predetermined portions of the first insulating layers by etching the second insulating layers; and wet-etching the first insulating layers and the non-etched portions of the second insulating layers. In the present invention, an isolating region in the narrow trench is formed without voids by regulating the deposition/etching ratio during the formation of an insulating layer in a trench.
REFERENCES:
patent: 4551911 (1985-11-01), Sasaki et al.
patent: 5192706 (1993-03-01), Rodder
patent: 5242853 (1993-09-01), Sato et al.
patent: 5498565 (1996-03-01), Gocho et al.
patent: 5504033 (1996-04-01), Bajor et al.
patent: 5721173 (1998-02-01), Yano et al.
patent: 5763315 (1998-06-01), Benedict et al.
Fourson George
LG Semicon Co. Ltd.
LandOfFree
Method of forming isolating region does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming isolating region, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming isolating region will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1455210