Method of forming isolated integrated injection logic gate

Details Method of forming isolated integrated injection logic gate Method of forming isolated integrated injection logic gate

2000-08-15

2001-05-15

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Complementary bipolar transistors

C438S309000, C438S322000, C438S324000, C438S325000

Reexamination Certificate

active

06232193

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor devices, and more particularly to such devices including an integrated injection logic gate.
BACKGROUND OF THE INVENTION
With reference to
FIGS. 1 and 2
, there is illustrated a schematic of a basic integrated injection logic gate
10
which comprises a multi-collector upside down NPN transistor
11
, and a lateral PNP transistor
12
serving as a current source. The collector
18
and the base
19
of the current source
12
are connected to the base
14
and emitter
8
of the upside down NPN transistor
11
, respectively. The current source thereby injects carriers through the base region
19
of the lateral PNP transistor
12
into the base region
14
of the upside down NPN transistor
11
. When integrated, the base
14
of the NPN transistor
11
is common to the collector
18
of the current source, and the base
19
of the current source is common to the emitter
8
of the NPN transistor. The emitter
9
of the current source
12
is the injector. In such devices, the common base
19
of the current source
12
and the emitter
8
of the NPN transistor
11
is a buried N layer
4
and epitaxial layer
8
that is connected to a supply voltage (ground). Normally, several collectors are required to implement logic functions.
FIG. 2
illustrates a known I
2
L device with a I-substrate
2
and having a buried n+ region
4
, an n-epitaxial region
8
, having a deeply buried n region (DN)
6
with n+ region
7
formed thereon. The base
14
is located in the same active area as the collectors
13
. A metal layer
17
is used to contact each of the collectors. The metal layer can be silicide provided over selected areas of the device in a salicided, i.e. a self-aligned silicide, bipolar process. A metal layer or silicide is often used to connect all of the p+ base regions on top of the silicon surface. A problem with a structure such as that illustrated in
FIG. 2
is that there is recombination current in the salicided base region which causes current loss and adversely affects the current gain. For a bipolar process which does not have silicide in the process, if a heavily doped p+ implant is used to reduce the base resistance, the same current loss problem exists in the base region.
SUMMARY OF THE INVENTION
An object of this invention is to provide an integrated injection logic (“I
2
L”) device in which the above enumerated problems associated with the conventional devices are obviated.
According to the invention, an integrated injection logic device is provided in which each collector of the I
2
L gate is isolated by a field oxide (“FOX”), or by other suitable isolation such as, for example, an isolation trench. As a result of said isolation, the collectors cannot talk to each other. The connection of the base to the collectors, between the base contact region and the bottom of the collectors, is made underneath the field oxide using a buried p type layer (TN
3
in the Figures illustrating the invention). Because both silicide and heavy implant p+ implant are present at the base contact point only, (see FIG.
3
B), the recombination current is reduced. This reduces the current loss when compared to the current loss of the known device. Additionally, current gain is also improved by placing a deep base (such as for example, TN
3
implanted region
85
) close to the emitter (such as for example, buried n layer
40
). The area of the base and the area of the collectors is decoupled, i.e. one can adjust the base to collector areas and the base contact area independently to control the total base current, thus allowing more freedom in layout optimization of the I
2
L gate and allowing more freedom in optimizing the gain of the I
2
L gate.
Thus the objects of the invention are accomplished by removing the base region accompanying each collector region in the same active area, whereby the recombination current component is reduced and the gain of the I
2
L gate is enhanced. According to the invention, each collector of the I
2
L gate is substantially completely isolated within a gate by a field oxide and the base linkup is done underneath the field oxide with a remote contact. Therefore, an additional metal layer to connect all the base regions together is not required. This (i) avoids the need for an extra metallization to connect bases and (ii) reduces the recombination current in the prior art I
2
L gate associated with the base region accompanying the etch collector region, thereby increasing the gain for the improved device.
U.S. Pat. No. 4,433,471 discloses a method for the formation of high density memory cells using ion implantation techniques. In this process a thick oxide, not field oxide, is used to isolate different emitters; the base link is situated under the thick oxide, and the linkup between a LPNP and the base region appears to happen under the thick oxide. However, in such devices, polysilicon is not used and the device is devoid of polysilicon protection against the p+ implant going into the collector region. Therefore, the base implant must be done through photoresist. In addition, two base implants are used. One is deep and the other is a heavy p+ shallow implant to reduce the base resistance. However, this heavy p+ shallow base implant causes additional recombination current loss. Furthermore, DN implants are not used to isolate one memory cell from another, and the base width of the LNPN is determined by the thick oxide width, leading to much larger structures than envisioned and achieved herein.


REFERENCES:
patent: 5591656 (1997-01-01), Sawada
patent: 5661066 (1997-08-01), Takemoto et al.
patent: 6008524 (1999-12-01), Gomi

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