Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-06-21
2002-11-12
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S623000, C438S624000, C438S706000, C438S781000, C438S787000
Reexamination Certificate
active
06479399
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming an interlevel dielectric layer of a semiconductor device.
2. Description of the Related Art
As the integration density of semiconductor devices has increased, the size of lines has been reduced and the gap between lines has been narrowed. An interlevel dielectric layer formed between lines is required to serve as insulation and should not be changed in a subsequent thermal process. Also, the interlevel dielectric layer is required to have an excellent flatness, and a low dielectric constant to reduce parasitic capacitance between adjacent lines. However, a conventional dielectric layer formed between lines, such as an undoped silicate glass (USG) layer, high density plasma (HDP) layer or plasma enhanced-tetra ethyl ortho silicate (PE-TEOS) layer, has an inferior gap fill property. Namely, in a deposition process for forming an interlevel dielectric layer, voids or crevices are generated therein.
SUMMARY OF THE INVENTION
The present invention is therefore directed to forming an interlevel dielectric layer which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.
To solve the above problems, it is an object of the present invention to provide a method of forming an interlevel dielectric layer of a semiconductor device capable of filling the gap between conductive lines to prevent the generation of voids or cracks.
Accordingly, to achieve the above object, in the method of forming the interlevel dielectric layer of the semiconductor device, a conductive line is formed on a semiconductor substrate. Sequentially, a polysilazane-family spin on glass (SOG) layer is deposited on the semiconductor substrate on which the conductive line is formed. Next, the polysilazane-family SOG layer is baked and then etched back until the upper part of the conductive line is exposed. A silicon oxide layer is formed by thermally treating the polysilazane-family SOG layer remaining after the etch back process. The conductive line has a structure in which a hard mask layer made of silicon nitride is stacked on a conductive layer made of polysilicon, silicide or polycide. A spacer is formed at the side wall of the conductive line between the formation of the conductive line and the deposition of the SOG layer. The polysilazane-family SOG layer is soft baked at a temperature of about 50-300° C. and hard baked at a temperature of about 300-500° C. In etching back the polysilazane-family SOG layer a C-F-family gas, which gives an etch selectivity ratio of the polysilazane-family SOG layer to the silicon nitride layer of more than 10 to 1 and has a C to F ratio of at least 0.5, is used as an etch back gas. It is preferable that the C-F family gas is one selected from the group consisting of C
5
F
8
, C
4
F
8
, C
4
F
6
, or CH
2
F
2
. The thermal treatment is performed under an atmosphere of O
2
, H
2
O or a combination of both at a temperature of about 600-1200° C. for about 10-20 minutes. After the thermal treatment, a dielectric layer is deposited and planarized.
These and other objects of the present invention will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating the preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
REFERENCES:
patent: 5310720 (1994-05-01), Shin et al.
Jeon Jeong-sic
Min Gyung-jin
Park Wan-jae
Nguyen Ha Tran
Volentine & Francos, PLLC
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