Method of forming interlevel dielectric for integrated circuits

Details Method of forming interlevel dielectric for integrated circuits Method of forming interlevel dielectric for integrated circuits

1992-10-30

1994-09-06

Quach, T. N.

Fishing, trapping, and vermin destroying

437195, 437228, 437978, 748DIG118, H01L 21316

Patent

active

053447972

ABSTRACT:
A method of forming an interlevel dielectric suitable for use with semiconductor integrated circuits is disclosed. The dielectric illustratively includes a triple layer sandwich of ozone-TEOS formed between two layers of plasma-enhanced TEOS. The dielectric is capable of filling high-aspect ratio trenches between runners. The ozone-TEOS is formed at a high pressure (approximately 90 Torr) to reduce hydrogen absorption. The reduced-hydrogen content ozone-TEOS is less susceptible to moisture formation and, therefore, presents less risk of degrading subsequently formed aluminum runners.

REFERENCES:
patent: 4872947 (1989-10-01), Wang et al.

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