Method of forming interconnections in an integrated circuit

Details Method of forming interconnections in an integrated circuit Method of forming interconnections in an integrated circuit

1998-07-17

2000-04-18

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257113, 257116, 257228, 257257, 257290, 257184, 257432, 257437, 257451, 257461, 257921, 257394, 438792, 438621, 438622, 438635, 438637, 438783, 359269, 359273, H01L 2348, H01L 2352, H01L 2940

Patent

active

060518847

ABSTRACT:
The invention provides a method for producing wiring and contacts in an integrated circuit including the steps of forming insulated gate components on a semiconductor substrate; applying a photo-reducible dielectric layer to cover the substrate; etching holes and forming contacts; photo-reducing the dielectric to increase its conductivity; covering the resulting structure with an interconnect layer; etching the interconnect layer to define wiring in electrical contact with the contacts; and oxidizing the dielectric to reduce its conductivity.

REFERENCES:
patent: 3553533 (1971-01-01), Haberecht
patent: 4457950 (1984-07-01), Fujita et al.
patent: 5459098 (1995-10-01), Maya
patent: 5517031 (1996-05-01), Wei et al.
patent: 5559055 (1996-09-01), Chang et al.
patent: 5808855 (1998-09-01), Chan et al.
French Search Report from French Patent Application 96 0618, filed May 7, 1996.
French Search Report from French Patent Application 96 06019, filed May 7, 1996.
Solid State Communications, vol. 86, No. 10, 1993, G.B., pp 619-623, B. Pashmakov, et al., "Photoreduction and Oxidation of Amorphous Indium Oxide".
Pashmakov et al., "Photoreduction and Oxidation of Amorphous Indium Oxide," Solid State Communications, vol. 86, No. 10, pp. 619-623, Apr. 6, 1993.

Affiliated with

Also associated with

Rating

Method of forming interconnections in an integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming interconnections in an integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming interconnections in an integrated circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2338194