Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2002-01-15
2004-03-23
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S122000, C438S124000, C438S126000
Reexamination Certificate
active
06709897
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of forming an integrated circuit package having an upward-facing chip cavity. More particularly, the present invention relates to a method of forming an integrated circuit package that combines the processing of substrate board with the packaging of a silicon chip inside an upward-facing cavity.
2. Description of Related Art
As a result of rapid progress in integrated circuit (IC) fabrication techniques and expansion in applications, various types of IC package have been developed. One of the packages is ball grid array (BGA). To form a BGA package, a silicon chip is attached to a substrate and a few solder balls are planted on the substrate. The BGA package makes electrical connection with external devices through the solder balls. In general, there are two major ways of connecting a silicon chip to a substrate. The silicon chip is connected to the substrate either through bumps on a flip chip package or through bonded wires. Before attaching the silicon chip to the substrate, necessary circuit trace and connecting pads for connecting with the silicon chip must be patterned out on the substrate. However, the aforementioned types of chip-to-substrate connections produce a few problems.
To join a chip to the substrate in a flip-chip package, a layer of flux must be applied to the surface of the connecting pads and the chip package must be carefully aligned with the linking pads before applying heat to re-solder all contact points. Since re-soldering in this manner is not highly reliable, partial connection between some of the input/output contacts (bonding pads) on the chip and their corresponding connecting pads on the substrate may result. Repairing such partial contacts once they are formed is usually difficult. In addition, underfill material must be applied to fill up the space between the chip and the substrate in the process of forming the flip-chip package. The filling process demands high ingenuity because air bubbles might be entrenched inside the plastic leading to a low product yield.
On the other hand, if contacts between a silicon chip and a substrate are provided by gold wires, wire bonding strength, connective reliability and signal delay are all problems that need to be considered. Moreover, air bubbles may be trapped inside the plastic material in a subsequent molding process leading to further reliability problems. In addition, spatial limitations also restrict the wire-bonding density.
In brief, conventional chip-to-substrate attachment processes often lead to problems regarding the reliability of connection and the trapping of air bubbles inside underfilling or molding material, especially for a fine-pitch design. Hence, yield of the package is lowered considerably.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of forming an integrated circuit package having an upward-facing chip cavity capable of increasing production yield.
A second object of this invention is to provide a method of forming an integrated circuit package having an upward-facing chip cavity that ensures reliable connections between contact points on a silicon chip and corresponding connecting pads on a substrate board.
A third object of this invention is to provide a method of forming an integrated circuit package having an upward-facing chip cavity that avoids the trapping of bubbles inside underfilling and molding material.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming an integrated circuit package with an upward-facing chip cavity. First, a substrate is provided. A first opening that passes through the substrate is formed. A thermal conductive layer is joined to the lower surface of the substrate through the application of pressure. The first opening exposes a portion of the thermal conductive layer. A silicon chip is attached to the exposed upper surface of the thermal conductive layer inside the first opening. The silicon chip has an active surface and a backside surface. The active surface further includes a plurality of bonding pads thereon. The backside of the silicon chip is in contact with the upper surface of the thermal conductive layer so that the chip is fixed in position. A dielectric layer is formed to fill the first opening and cover the substrate as well as the active surface and the bonding pads of the silicon chip. The dielectric layer and the substrate are patterned to form a plurality of second openings that expose the bonding pads. A plurality of third openings that passes through the dielectric layer and the substrate and exposes a portion of the thermal conductive layer is formed. A metallic layer is formed over the exposed surface of the second openings, the third openings and the dielectric layer by electroplating. The metallic layer is patterned to form a patterned metallic layer. A patterned solder resistant layer is formed over the patterned metallic layer. The patterned solder resistant layer has a plurality of fourth openings that expose a portion of the patterned metallic layer. A solder ball planting operating is carried out to place one solder ball over each fourth opening. The solder ball is heated to form electrical connection between the solder ball and the patterned metallic layer.
This invention also provides an alternative method of forming an integrated circuit package having an upward-facing chip cavity. First a substrate having a cavity section therein is provided. A silicon chip is attached to the cavity section of the substrate. The silicon chip has an active surface and a backside surface. The active surface further includes a plurality of bonding pads thereon. The backside of the silicon chip is in contact with the cavity section of the substrate so that the chip is fixed in position. A patterned dielectric layer is formed to fill the cavity section and cover the active surface and the bonding pads of the silicon chip. The patterned dielectric layer has a plurality of second openings and a plurality of third openings. The second openings expose the bonding pads while the third openings pass through the patterned dielectric layer and expose a portion of the substrate. A metallic layer is formed over the exposed surface of the second openings, the third openings and the dielectric layer by electroplating. The metallic layer is patterned to form a patterned metallic layer. A patterned solder resistant layer is formed over the patterned metallic layer. The patterned solder resistant layer has a plurality of fourth openings that expose a portion of the patterned metallic layer. A solder ball planting operating is carried out to place one solder ball over each fourth opening. The solder ball is heated to form electrical connection between the solder ball and the patterned metallic layer.
One major aspect of this invention is the combination of substrate processing and chip packaging leading to a greater flexibility in manufacturing.
A second major aspect of this invention is the formation of a patterned dielectric layer to expose the bonding pads on the chip before performing an electroplating for connecting the bonding pads and the substrate pads electrically. Hence, superior electrical contact between the chip and the substrate is formed and reliable connection between the chip and the substrate is ensured.
A third major aspect of this invention is the formation of the patterned dielectric layer before coating a layer of metal over the patterned dielectric layer by electroplating. This sequence of processing steps prevents the formation of any bubbles inside the patterned dielectric layer. Consequently, conventional problems caused by trapped bubbles inside underfilling or molding material are entirely avoided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation o
Cheng David C. H.
Cheng Jao-Chin
Fan Chih-Peng
Chaudhuri Olik
J.C. Patents
Nguyen Khiem
Unimicron Technology Corp.
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