Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support
Reexamination Certificate
2002-02-15
2003-01-14
Talbott, David L. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Insulative housing or support
C438S108000, C438S118000, C438S125000, C438S127000
Reexamination Certificate
active
06506632
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of forming an integrated circuit package having a downward-facing chip cavity. More particularly, the present invention relates to a method of forming an integrated circuit package that combines the processing of substrate board with the packaging of a silicon chip inside a downward-facing cavity.
2. Description of Related Art
As a result of rapid progress in integrated circuit (IC) fabrication techniques and expansion in applications, various types of IC package have been developed. One of the packages is ball grid array (BGA). To form a BGA package, a silicon chip is attached to a substrate and a few solder balls are planted on the substrate. The BGA package makes electrical connection with external devices through the solder balls. In general, there are two major ways of connecting a silicon chip to a substrate. The silicon chip is connected to the substrate either through bumps on a flip chip package or through bonded wires. Before attaching the silicon chip to the substrate, necessary circuit trace and connecting pads for connecting with the silicon chip must be patterned out on the substrate. However, the aforementioned types of chip-to-substrate connections produce a few problems.
To join a chip to the substrate in a flip-chip package, a layer of flux must be applied to the surface of the connecting pads and the chip package must be carefully aligned with the linking pads before applying heat to re-solder all contact points. Since re-soldering in this manner is not highly reliable, partial connection between some of the input/output contacts (bonding pads) on the chip and their corresponding connecting pads on the substrate may result. Repairing such partial contacts once they are formed is usually difficult. In addition, underfill material must be applied to fill up the space between the chip and the substrate in the process of forming the flip-chip package. The filling process demands high ingenuity because air bubbles might be entrenched inside the plastic leading to a low product yield.
On the other hand, if contacts between a silicon a chip and a substrate are provided by gold wires, wire bonding strength, connective reliability and signal delay are all problems that need to be considered. Moreover, air bubbles may be similarly trapped inside the plastic material in a subsequent molding process leading to further reliability problems.
In brief, conventional chip-to-substrate attachment processes often lead to problems regarding the reliability of connection and the trapping of air bubbles inside underfilling or molding material, thereby lowering the yield of the package.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of forming an integrated circuit package having a downward-facing chip cavity capable of increasing production yield.
A second object of this invention is to provide a method of forming an integrated circuit package having a downward-facing chip cavity that ensures reliable connections between contact points on a silicon chip and corresponding connecting pads on a substrate board.
A third object of this invention is to provide a method of forming an integrated circuit package having a downward-facing chip cavity that avoids the trapping of bubbles inside underfilling and molding material.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming an integrated circuit package with a downward-facing chip cavity. First, a substrate comprising an insulating core layer and a conductive layer is provided. The conductive layer is formed over the lower surface of the insulating core layer. A first opening is formed in the substrate passing through both the insulating core layer and the conductive layer. An adhesive tape is attached to the surface of the conductive layer. A silicon chip is attached to the exposed adhesive tape surface at the bottom of the first opening. The chip has an active surface and a back surface. The chip further includes a plurality of bonding pads on the active surface. The back surface of the chip is attached to the adhesive tape. A patterned dielectric layer is formed filling the first opening and covering a portion of the adhesive tape, the active surface, the bonding pad and the insulating core layer. The patterned dielectric layer has a plurality of second openings and third openings. The second openings expose the bonding pads on the chip. The third openings pass through the patterned dielectric layer, the insulating core layer and the conductive layer. A metallic layer is formed over the exposed surface of the second openings and the third openings as well as the upper surface of the patterned dielectric layer by electroplating. The adhesive tape is removed to expose the conductive layer, backside of the chip and a portion of the patterned dielectric layer. The metallic layer and the conductive layer are patterned. A patterned solder resistant layer is formed over the metallic layer and the conductive layer. The patterned solder resistant layer has a plurality of fourth openings that expose a portion of the conductive layer. A solder ball implant is conducted to attach solder balls to the conductive layer so that the solder balls and corresponding sections of the conductive layer are electrically connected.
One major aspect of this invention is the combination of substrate processing and chip packaging leading to a greater fluidity in manufacturing.
A second major aspect of this invention is the formation of a patterned dielectric layer to expose the bonding pads on the chip before performing an electroplating for connecting the bonding pads and the substrate pads electrically. Hence, superior electrical contact between the chip and the substrate is formed and reliable connection between the chip and the substrate is ensured.
A third major aspect of this invention is the formation of the patterned dielectric layer before coating a layer of metal over the patterned dielectric layer by electroplating. This sequence of processing steps prevents the formation of any bubbles inside the patterned dielectric layer. Consequently, conventional problems caused by trapped bubbles inside underfilling or molding material are entirely avoided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
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patent: 6093584 (2000-07-01), Fjelstad
patent: 6093970 (2000-07-01), Ohsawa et al.
patent: 6399418 (2002-06-01), Glenn et al.
Cheng David C. H.
Cheng Jao-Chin
Fan Chih-Peng
Talbott David L.
Unimicron Technology Corp.
Zarneke David A.
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