Method of forming high speed, high voltage fully isolated bipola

Details Method of forming high speed, high voltage fully isolated bipola Method of forming high speed, high voltage fully isolated bipola

1993-06-03

1994-09-06

Thomas, Tom

Fishing, trapping, and vermin destroying

437 55, 437 61, 437 62, 148DIG85, 148DIG150, H01L 21265

Patent

active

053447859

ABSTRACT:
A method of manufacturing various types of silicon devices, such as complementary bipolar PNP and NPN transistors, in a Silicon On Insulator ("SOI") Integrated Circuit ("IC"), the SOI IC having a substrate, a buried insulating layer disposed above the substrate, and a silicon device layer disposed above the insulating layer. Vertical transistors may be formed in the device layer such that each transistor is fully dielectrically isolated from another and also from other similarly manufactured silicon devices in the silicon device layer.

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