Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1999-04-15
2001-03-20
Nguyen, Tuan H. (Department: 2815)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S399000, C438S637000
Reexamination Certificate
active
06204143
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor fabrication processing and, more particularly, to a method for forming high aspect ratio structures, such as contact interconnects and capacitors for semiconductor devices.
BACKGROUND OF THE INVENTION
The continuing trend of scaling down integrated circuits has forced the semiconductor industry to consider new techniques for fabricating precise components at sub-micron levels. Along with the need for smaller components, there has been a growing demand for devices requiring less power consumption. In the manufacture of memory devices, these trends have led the industry to refine approaches to achieve thinner capacitor cell dielectric and surface enhanced storage capacitor electrodes.
As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairly constant rate. In semiconductor devices it may be advantageous to build contact plugs for interlayer connections with high aspect ratio structures as circuit density will be enhanced. Also, in dynamic random access memory (DRAM) devices it is essential that storage node capacitor cell plates be large enough to exhibit sufficient capacitance in order to retain an adequate charge in spite of parasitic capacitance and noise that may be present during circuit operation. The issue of maintaining storage node capacitance is particularly important as the density of DRAM arrays continues to increase for future generations of memory devices. The ability to densely pack storage cells while maintaining required capacitance levels is a crucial requirement of semiconductor manufacturing technologies if future generations of expanded memory array devices are to be successfully manufactured.
The present invention develops a method to form high aspect ratio structures, such as interconnecting contact plugs and storage capacitors. Greater circuit density will be possible as the fabricated device will benefit from deep contact plug interconnects and/or increased storage electrode surface areas than are attainable in conventional processing methods.
SUMMARY OF THE INVENTION
The present invention teaches a method to form a high aspect ratio structure for a semiconductor device, such as an interconnect or a storage capacitor plate for memory devices. The interconnect structure is conductive is formed by using multiple building levels that successfully produce a structure that has an aspect ratio such that the length is greater than the width and the opposing walls are substantially parallel (i.e., the opposing walls of the structure intersects an underlying surface at an angle that is 88° or greater).
Each building level comprises the steps of 1) forming a planarized layer of insulation material, 2) forming an opening therein that is aligned to the underlying sacrificial material and then 3) forming a planarized sacrificial material into the opening. These steps may be repeated or even deleted as desired in order to obtain as deep (or as tall) of a structure as needed for a given device.
REFERENCES:
patent: 5821164 (1998-10-01), Kim et al.
patent: 5930672 (1999-07-01), Yamamoto
patent: 6033977 (2000-03-01), Gutsche et al.
patent: 6074912 (2000-06-01), Liu et al.
patent: 6080653 (2000-06-01), Givens
DeBoer Scott
Roberts Ceredig
Micro)n Technology, Inc.
Nguyen Tuan H.
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