Method of forming ferroelectric capacitor in semiconductor...

Details Method of forming ferroelectric capacitor in semiconductor... Method of forming ferroelectric capacitor in semiconductor...

2001-12-07

2002-07-09

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S240000

Reexamination Certificate

active

06417012

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor fabrication technique. Particularly, the present invention relates to a method for forming a ferroelectric capacitor, in which a ferroelectric thin film is used as the dielectric medium. More specifically, the present invention relates to a method for forming a ferroelectric capacitor, in which there is used a strontium(Sr)-bismuth(Bi)-tantalum(Ta)(SBT)-based ferroelectric thin film such as Sr
x
Bi
y
Ta
2
O
9
(to be called ‘SBT’ below) or Sr
x
Bi
y
(Ta
i
Nb
j
)
2
O
9
(to be called ‘SBT(N)’ below) as the dielectric medium.
BACKGROUND OF THE INVENTION
Ferroelectric material has a high dielectric constant, and shows a nonvolatile polarization, and therefore, it is used as a semiconductor material. That is, ferroelectric material has become a new semiconductor material for a high density Gb or more) DRAM (dynamic random access memory), and for the ferroelectric memory (FeRAM).
Depending upon the method of connection to the substrate, the ferroelectric capacitor is classified as a NPP (non-plug poly) structure or a PP (plug poly) structure. First, in the ferroelectric capacitor of the NPP structure, the junction of the MOS transistor is connected to the upper electrode through a metal wiring, so that the upper electrode can serve as a storage node and the lower electrode can serve as a cell plate.
On the other hand, in the ferroelectric capacitor of the PP structure, the junction of the MOS transistor is connected to the lower electrode through a polysilicon plug, so that the lower electrode can serve as a storage node, and the upper electrode can serve as a cell plate.
If the density of the device is considered, the ferroelectric capacitor of the PP structure is preferable to the ferroelectric capacitor of the NPP structure. However, if the PP structure is adopted, a process difficulty is encountered. That is, when forming the upper and lower electrodes and the dielectric medium, and when carrying out the post thermal process, oxygen is diffused to form a low dielectric constant silicon oxide (SiO
2
) on the polysilicon plug. As a result, most of the externally supplied voltage is supplied to the low dielectric constant silicon oxide, thereby forming a fatal defect.
Meanwhile, the SBT, or SBT(N), is formed by carrying out a heat treatment for realizing crystallization, so that superior electrical properties can be obtained. The crystallizing heat treatment includes a rapid thermal annealing (RTA) and a furnace annealing. The RTA is carried out under an oxygen atmosphere so as to remove a metal-containing organic material and so as to realize a nuclear formation, while the furnace annealing is carried out for the growth of grains.
Under this condition, the RTA (rapid thermal annealing) is carried out at a temperature of about 725° C., and the furnace annealing is carried out at a temperature of about 800° C. Therefore, if a certain polarization value is to be obtained, there is a problem in that a thermal budget is imposed. Increase of the thermal budget aggravates the formation of the silicon oxide in the PP structure. Consequently, the barrier metal film is degraded, thereby reducing the reliability of the device.
SUMMARY OF THE INVENTION
The present invention is intended to overcome the above described disadvantages of the conventional technique.
Therefore it is an object of the present invention to provide a method of forming a ferroelectric capacitor in a semiconductor device, in which the thermal burden can be reduced by using an SBT-based ferroelectric thin film.
In achieving the above object, the method for forming a ferroelectric capacitor in a semiconductor device according to the present invention includes the steps of forming a strontium-bismuth-tantalum oxide film on a semiconductor substrate, with a conductive film for a lower electrode having been formed on the semiconductor substrate (first step); flowing an NH
3
gas at a stabilizing step of a rapid thermal annealing so as to reduce organic materials bonded with metal elements of the strontium-bismuth-tantalum oxide film (second step); flowing an oxide gas at a temperature of 450~650° C. at an annealing step of the rapid thermal annealing so as to induce a perovskite nuclear formation in the strontium-bismuth-tantalum oxide film (third step); and carrying out a furnace annealing so as to induce a grain growth in the strontium-bismuth-tantalum oxide film (fourth step).
Preferably, the second step is carried out at a temperature of 300~450°C.
Preferably, the oxide gas is at least one selected from the group consisting of: O
2
, N
2
O, H
2
O, H
2
O
2
and O
3
.
Preferably, the strontium-bismuth-tantalum oxide film is Sr
x
Bi
y
Ta
2
O
9
or Sr
x
Bi
y
(Ta
i
Nb
j
)
2
O
9
.


REFERENCES:
patent: 6096597 (2000-08-01), Tsu et al.
patent: 6245580 (2001-06-01), Solayappan et al.
patent: 6251720 (2001-06-01), Thakur et al.
patent: 6274454 (2001-08-01), Katori
patent: 2002/0045358 (2002-04-01), Weimer et al.

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