Method of forming electrode/wiring layer

Metal working – Method of mechanical manufacture – Assembling or joining

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29571, 29578, 148 15, 357 59, 357 65, 357 67, 357 71, 427 88, 427 90, H01L 2124, H01L 2946, H01L 2128

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045383448

ABSTRACT:
An interconnection structure including an electrode/wiring layer can be formed on a semiconductor substrate by forming on the semiconductor substrate an insulating structure having at least one recess in a surface thereof. At least one polycrystalline silicon layer is formed to fill the recess of the insulating structure. Then, an aluminum layer is formed to cover a surface of the insulating structure and a surface of the polycrystalline silicon layer. The polycrystalline silicon in the polycrystalline silicon layer and the aluminum in a portion of the aluminum layer which corresponds to the polycrystalline silicon layer are converted into a single alloy by heating to form an electrode/wiring layer comprising the single alloy in the recess and connected to a remaining portion of the aluminum layer.

REFERENCES:
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patent: 3918149 (1975-11-01), Roberts
patent: 3996656 (1976-12-01), Cook
patent: 4291322 (1981-09-01), Clemens et al.
patent: 4316209 (1982-02-01), Ho et al.
patent: 4322453 (1982-03-01), Miller
patent: 4358891 (1982-11-01), Roesner
patent: 4361599 (1982-11-01), Wourms
Kircher et al., "Fabricating a Gate Field-Effect Transistor" IBM Tech. Disc. Bull., vol. 13, No. 3, Aug. 1970, pp. 646-648.
Krausse, "Spreading Resistance Measurements on Silicon with Non-Blocking Aluminum-Silicon Contacts", NBS Special (Pub. 400-10 June 13-14, 1974, pp. 109-122.

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