Method of forming edge-sealed multi-layer structure while protec

Details Method of forming edge-sealed multi-layer structure while protec Method of forming edge-sealed multi-layer structure while protec

1987-06-15

1988-07-26

Roy, Upendra

Fishing, trapping, and vermin destroying

357 24, 357 45, 357 91, 437 59, 437 60, 148DIG82, H01L 2194, H01L 2122, H01L 2978

Patent

active

047600349

ABSTRACT:
A process for forming a DRAM cell having a capacitor adjacent a field effect transistor (FET), wherein the FET fabrication area is protected from adverse effects of the capacitor formation. The process is misalignment tolerant and provides FETs with appreciably lower defects in the substrate beneath the FET. Additionally, the process eliminates the need to stop an etching operation on a thin capacitor dielectric layer.

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patent: 4350536 (1982-09-01), Nakano et al.
patent: 4391032 (1983-07-01), Schulte
patent: 4422885 (1983-12-01), Brower et al.
patent: 4466177 (1984-08-01), Chao
patent: 4536947 (1985-08-01), Bohr et al.
patent: 4603059 (1986-07-01), Kiyosomi et al.

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