Method of forming dual damascene structure

Details Method of forming dual damascene structure Method of forming dual damascene structure

2000-08-31

2002-08-27

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S723000, C438S724000, C438S694000, C438S689000, C438S660000, C438S672000

Reexamination Certificate

active

06440861

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 89116603, filed Aug. 17, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of forming a dual damascene structure. More particularly, the present invention relates to a method of forming a dual damascene opening capable of reducing the degree of interaction between low dielectric constant material and photoresist material.
2. Description of Related Art
The operating speed is often a principle consideration by customer to choose a particular brand of semiconductor products by customers. At present, major factors that may affect the operating speed of a device include the resistivity of conducting wires and parasitic capacitor of the inter-layer dielectric layer. To reduce wire resistance, low resistance metallic material is often used to form the conducting wires. To improve inter-layer parasitic capacitance, material having a low dielectric constant is frequently employed to form the insulation layer between metallic interconnects.
In general, conventional metallic interconnects are fabricated by forming a metal plug in a dielectric layer followed by depositing aluminum material over the metal plug to form an aluminum wire. Dual damascene technique is a low-cost, high-reliability method of fabricating the metallic lines of an integrated circuit. Moreover, the metallic material for forming the metallic interconnects in a dual damascene structure can be etched without much restriction. Hence, dual damascene techniques are frequently used to form low resistance copper wires for increasing the operating speed of circuit devices. As the level of integration of devices continues to increase, the use of low dielectric constant material to fabricate dual damascene structures is fast becoming a standard in the semiconductor industry.
FIGS. 1A through 1D
are schematic cross-sectional views showing the progression of steps for fabricating a conventional dual damascene structure. As shown in
FIG. 1A
, a substrate
100
having a metallic layer
102
therein is provided. A dielectric layer
104
, an etching stop layer
106
and a dielectric layer
108
are sequentially formed over the substrate
100
. A photoresist layer
110
is next formed over the dielectric layer
108
. Conventional photolithographic technique is applied to pattern the photoresist layer
110
so that location of a via opening is defined.
As shown in
FIG. 1B
, using the photoresist layer
110
as an etching mask, the dielectric layer
108
, the etching stop layer
106
and the dielectric layer
104
are sequentially etched to form a via opening
112
that exposes the metallic layer
102
. The photoresist layer
110
is removed and then another photoresist layer
114
is formed over the substrate
100
. Conventional photolithographic technique is again applied to pattern the photoresist layer
114
so that location of a trench is defined.
As shown in
FIG. 1C
, using the photoresist layer
114
as an etching mask and the etching stop layer
106
as an etching stop, the dielectric layer
108
is etched to form a trench
116
. In the subsequent step, the photoresist layer
114
is removed and then metal is deposited into the trench
116
and the via opening
112
to form a metallic layer
118
. Ultimately, a dual damascene structure having a cross-sectional profile as shown in
FIG. 1D
is formed.
As the level of integration continues to increase, parasitic capacitance that results from the inter-metal dielectric layer will be intensified. In particular, low dielectric constant material is frequently employed to form the inter-metal dielectric layer in the manufacturing of deep sub-micron devices so that effects due to resistance-capacitance time delay is reduced. However, common photoresist material is composed of high molecular weight substances and most high dielectric constant material is composed of organic high molecular weight compounds. Consequently, in the photolithographic patterning of the photoresist layers
110
and
114
, organic low dielectric constant material may react chemically with the photoresist material. The resultant products of the reactions may adhere to the surface of a dual damascene contact to form a residue that is impossible to remove in a subsequent cleaning operation. Furthermore, before the dielectric layer
108
is etched to form the trench
116
, photoresist material is often deposited into the via opening
112
to serve as a hard mask so that the metallic layer
102
is protected. This photoresist material often reacts with nearby low dielectric constant material to form a residue. The residue damages the ideal profile of a dual damascene structure and affects the uniformity of subsequently formed copper seeding layer. A non-linear copper seeding layer often result in the formation of low-quality copper lines.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of forming a dual damascene structure capable of lowering parasitic effect by using low dielectric constant material so that highly integrated device circuits are formed. In addition, the method is capable of preventing any chemical reaction between photoresist and dielectric material to form difficult-to-remove residues on the sidewalls of via openings. Hence, an ideal profile of the dual damascene structure can be preserved.
A second object of this invention is to provide a method of forming a dual damascene structure that does not require the formation of an etching barrier layer. Instead, differences in etching rates between two low dielectric constant dielectric layer is utilized to form the opening of the dual damascene structure so that processing steps are saved.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a dual damascene structure. A first dielectric layer and a second dielectric layer are sequentially formed over a substrate. A first photoresist layer is formed over the second dielectric layer. Photolithographic and etching operations are conducted to remove a portion of the second dielectric layer and the first dielectric layer so that a via opening is formed. A conformal third dielectric layer is coated over the surface of the second dielectric layer and the interior surface of the via opening. The conformal third dielectric layer forms a liner dielectric layer. A second photoresist layer is formed over the second dielectric layer and then the second photoresist layer is patterned. Using the patterned second photoresist layer as a mask, a portion of the second dielectric layer is removed to form a trench. The patterned second photoresist layer is removed. Conductive material is deposited over the substrate to fill the via opening and the trench. Finally, chemical-mechanical polishing is conducted to remove excess conductive material above the second dielectric layer. If the conductive material is copper, a copper seeding layer needs to form on the surface of the second dielectric layer, the via opening and the trench before the deposition of copper.
Since the surface of the second dielectric layer is not protected by any layer when the first photoresist layer is deposited, difficult-to-remove residues will form on the surface of the second dielectric layer. Hence, a non-uniform copper seeding layer is formed on the interface with the second dielectric layer. On the other hand, the sidewalls and bottom of both the via opening and trench are protected by the liner dielectric layer. Thus, an ideal profile is preserved and subsequent copper deposition is facilitated. However, any non-uniformity in the copper layer is finally removed by the planarization of the copper layer through chemical-mechanical polishing.
In the embodiment of this invention, the liner dielectric layers serve as a partition that separates the photoresist material from the low dielectric constant material during ph

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