Method of forming crystalline silicon film

Single-crystal – oriented-crystal – and epitaxy growth processes; – Processes of growth from solid or gel state – Using heat

Reexamination Certificate

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C117S009000, C117S930000

Reexamination Certificate

active

06733584

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a crystalline silicon film formed on an insulating substrate of glass or the like, a semiconductor substrate of a single crystal silicon substrate or the like. Particularly, the present invention relates to a method of providing a crystalline silicon film in a preferable crystal state in which in a method of crystallizing an amorphous silicon film by annealing, horizontal growth is performed by using a catalyst element promoting crystallization (nickel or the like).
2. Description of Prior Art
A crystalline silicon film is a material indispensable in a semiconductor element of a thin film transistor or the like. It has been known in recent years that a silicon film having excellent crystalline performance can be obtained at a lower temperature in a short period of time by using a metal element having a function of promoting to crystallize an amorphous silicon film (catalyst element). Nickel (Ni), platinum (Pt), palladium (Pd), copper (Cu). silver (Ag), iron (Fe) or the like is effective as the catalyst element.
Particularly, there has been known a technology of providing a silicon film having a crystal structure preferable to an element by controlling a direction of crystal growth by nonselectively introducing a catalyst element (for example, Japanese Unexamined Patent Publication Nos. JP-A-7-45519 and JP-A-8-213634). The technology is referred to as a horizontal growth process. According lo the horizontal growth process, crystal grain boundaries are present in parallel with a direction of growth and the effect of the grain boundaries can be lowered to a limit thereof by making a direction of current of an element in parallel with the direction of growth. As a result, a characteristic equivalent to that of a single crystal material can be provided even for a polycrystal material.
A simple explanation will be given of the horizontal growth process. According to the horizontal growth process, a mask film of silicon oxide or the like is formed on an amorphous silicon film and a window is selectively formed in the film. A catalyst element is introduced from the window. In FIG.
1
(A), the window is designated by numeral
11
. Further, a film of a catalyst element per se or a compound thereof is formed by various methods of a sputtering process (Japanese Unexamined Patent Publication Nos. JP-A-7-45519 and JP-A-7-66425) a gas phase growth process (Japanese Unexamined Patent Publication No. JP-A-7-335548), a coating process (Japanese Unexamined Patent Publication No. JP-A-7-130652) and the like.
Further, when crystallization is performed by carrying out an annealing process, a region (horizontal growth region)
13
of crystalline silicon is widened centering on the window. This is caused since the catalyst element makes the amorphous silicon film crystallize while diffusing in the silicon film. Generally, the higher the temperature, the longer the time period, the further the crystallization is progressed. (FIG.
1
(A): details are described in Japanese Unexamined Patent Publications, mentioned above.)
By arranging the direction of horizontal growth in relation with a direction of flowing current in a semiconductor element such as a thin film transistor (TFT), the characteristic of the semiconductor can be promoted. That is, there are several variations in arranging TFT. One of the variations is shown by FIG.
3
. In
FIG. 3
, numeral
301
designates a window portion to which a catalyst element is added and a crystallized region
302
is widened by horizontal growth at the surrounding of the window centering on the window portion.
In this case, when the window portion
301
is provided with a rectangular shape, a horizontal growth region in an elliptic shape is formed as shown by FIG.
3
. in that case, a gate electrode
304
may be made substantially in parallel with the region
301
as shown by TFT
1
of FIG.
3
and crystal growth may be carried out in a direction of from a drain
305
to a source
303
or in a reverse direction thereof.
Further, as shown by TFT
2
of
FIG. 3
, a gate electrode
307
may be arranged substantially orthogonally to the region
301
and crystal growth may be carried out substantially simultaneously at a source
306
and a drain
308
. As a characteristic of TFT, according to the former method, ON current is large since directions of crystal growth and current are in parallel with each other and according to the latter method, OFF current is large since the directions of crystal growth and current are orthogonal to each other. (
FIG. 3
)
Further, the catalyst element may be added linearly by forming the window in a linear shape. FIGS.
4
(A) and
4
(B) show an example where catalyst adding regions
401
and
406
are provided in parallel with gate lines
402
and
407
in a circuit including a number of TFTs. FIG.
4
(A) corresponds to TFT
2
of
FIG. 3
where the catalyst element is added substantially orthogonally to gate electrodes of TFTs
403
through
405
. FIG.
4
(B) corresponds to TFT
1
of
FIG. 3
where the catalyst element is added substantially in parallel with gate electrodes of TFTs
408
through
410
. (FIGS.
4
(A) and
4
(B))
Such a control of the direction of crystal growth by means of the horizontal growth process is effective in a high degree semiconductor integrated circuit where elements to which mutually contradictory functions are requested, are formed on the same substrate.
FIG. 5
shows a block diagram of a monolithic type active matrix circuit used in a liquid crystal display. A source driver (row driver) and a gate driver (column driver) are installed as peripheral driver circuits.
Further, a number of pixel circuits comprising transistors for switching and capacitors are formed in the active matrix circuit (pixel) region and pixel transistors of the matrix circuit and the peripheral driver circuits are connected to each other by source lines and gate lines having numbers the same as a number of rows and a number of columns. High speed operation is requested to TFTs used in the peripheral circuits, particularly peripheral logical circuits of shift resistors and the like and accordingly, large current (ON current) and small dispersion are requested in selecting operation.
Meanwhile, it is requested to TFTs used in the pixel circuit that leakage current (also referred to as OFF current) is sufficiently low and dispersion is small in nonselecting operation, that is, when reverse bias voltage is applied to gate electrodes such that electric charge accumulated in capacitors are held for a long period of time. Specifically, it is requested that OFF current is equal to or lower than 1 pA and dispersion is within one digit. Conversely, rot so large ON current is needed.
As described above, TFTs having physically contradictory characteristics of high ON current and low leakage current, and small dispersion of these, are formed on the same substrate at the same time. However, it is easily understood that such requirements are very difficult to satisfy technically according to a normal crystallizing process.
By contrast, when the crystallizing direction is controlled by the horizontal growth process, these problems can be resolved (Japanese Unexamined Patent Publication No. JP-A-8-213634). In this way, the effectiveness of the horizontal growth process using the catalyst element is shown.
Ideally, when annealing operation is carried out at a higher temperature for a longer period of time, infinitely large horizontal growth can be provided, however, in that case, it has been observed that although the region of horizontal growth is enlarged, the quality of crystals is deteriorated as a whole. The behavior is shown by FIG.
1
(B). FIG.
1
(B) shows a behavior of continuing horizontal growth further from a state shown by FIG.
1
(A) where the horizontal growth region
13
is enlarged to a portion of an ellipse of a bold line designated by numeral
14
(in the case of FIG.
1
(A), a portion of an ellipse of a dotted line designate

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