Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2001-07-26
2002-08-20
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S253000, C438S687000
Reexamination Certificate
active
06436787
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods of fabricating a metal-insulator-metal capacitor, and more particularly, to methods of metal-insulator-metal capacitors integrated with copper damascene processes for mixed signal applications in the fabrication of an integrated circuit device.
(2) Description of the Prior Art
Capacitors are critical components in the integrated circuit devices of today. These passive components are often to be integrated with active bipolar or MOS transistors for analog and digital circuits. Capacitors of the types: polysilicon-insulator-polysilicon (PIP), polysilicon-insulator-polycide, polysilicon-insulator-metal (MIS), and metal-insulator-metal (MIM) capacitors have been used in the art. For mixed signal devices of 0.13 &mgr;m and below, copper damascene processes are necessary for high performance. Thus, the capacitor module needs to be integrated with copper metallization. Currently, the copper-integrated capacitor process is only for planar-type capacitors. For a given design rule, or cell size, a crown-shape capacitor provides a much larger effective electrode area than a planar-type capacitor and thus provides much larger capacitance for high-density future generation mixed signal applications. It is desired to provide a method for forming a crown-type MIM capacitor without complicating the existing process.
A number of patents address MIM capacitors. U.S. Pat. No. 6,159,787 to Aitken et al show a metal trench capacitor. U.S. Pat. No. 6,025,226 to Gambino et al discloses a MIM capacitor within a trench. However, leakage current may be a problem in this device. U.S. Pat. No. 6,159,793 to Lou and U.S. Pat. No. 6,069,051 to Nguyen et al disclose MIM capacitors. U.S. Pat. No. 6,117,747 to Shao et al shows a MOM capacitor and a dual damascene process, but the capacitor is not formed completely within a damascene opening.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the invention to provide an effective and very manufacturable process for producing a metal-insulator-metal capacitor.
Another object of the present invention is to provide a method for fabricating a metal-insulator-metal capacitor having increased capacitance.
Yet another object of the present invention is to provide a method for fabricating an increased capacitance metal-insulator-metal capacitor using an integrated copper damascene process.
A further object is to provide a method for fabricating an increased capacitance metal-insulator-metal capacitor using an integrated copper damascene process while saving process steps.
In accordance with the objects of this invention, a method for fabricating an increased capacitance metal-insulator-metal capacitor using an integrated copper damascene process is achieved. A contact node is provided overlying a semiconductor substrate. An intermetal dielectric layer is deposited overlying the contact node. A damascene opening is formed through the intermetal dielectric layer to the contact node. A first metal layer is formed on the bottom and sidewalls of the damascene opening and overlying the intermetal dielectric layer. A first barrier metal layer is deposited overlying the first metal layer. A capacitor dielectric layer is deposited overlying the first barrier metal layer. A second barrier metal layer is dpeosited overlying the capacitor dielectric layer. A second metal layer is formed overlying the second barrier metal layer and completely filling the damascene opening. The layers are polished back to leave the first metal layer, the dielectric layer, the first and second barrier metal layers, and the second metal layer only within the damascene opening wherein the first metal layer forms a bottom electrode, the dielectric layer forms a capacitor dielectric, and the second metal layer forms a top electrode to complete fabrication of a crown-type capacitor in the fabrication of an integrated circuit device.
REFERENCES:
patent: 5976928 (1999-11-01), Kirlin et al.
patent: 6025226 (2000-02-01), Gambino et al.
patent: 6069051 (2000-05-01), Nguyen et al.
patent: 6117747 (2000-09-01), Shao et al.
patent: 6150706 (2000-11-01), Thakur et al.
patent: 6153510 (2000-11-01), Ishibashi
patent: 6159787 (2000-12-01), Aitken et al.
patent: 6159793 (2000-12-01), Lou
patent: 6261895 (2001-07-01), Adkisson et al.
patent: 6320244 (2001-11-01), Alers et al.
Lee Tzyh-Cheang
Lin Chih-Hsien
Shih Wong-Cheng
Ting Wenchi
Wong Shyh-Chyi
Nguyen Tuan H.
Pike Rosemary L. S.
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