Method of forming conductor pattern on wiring board

Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Forming nonelectrolytic coating before depositing...

Reexamination Certificate

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C205S126000, C205S224000

Reexamination Certificate

active

06254758

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a conductor pattern on a wiring board such as a multiple layer wiring board.
2. Description of the Related Art
Referring to
FIG. 6
, a conventional method of forming a conductor pattern on a wiring board known in the prior art will be explained as follows.
First, an electroless copper plated layer
12
is formed on an insulating layer
10
of a wiring board as shown in Step (a) of FIG.
6
. In this case, the insulating layer includes an insulating layer which is interposed between conductor patterns formed on a multiple layer for the purpose of ensuring the electrical insulation between the conductor patterns. Further, the insulating layer includes a base material itself. These circumstances are the same in this specification hereinafter.
Next, a layer of plated resist
14
is patterned on the electroless copper plated layer
12
as shown in Step (b) of FIG.
6
.
Next, an electrolytic copper plated layer
16
is patterned and plated on the exposed electroless copper plated layer
12
as shown in Step (c) of
FIG. 6
, wherein the electroless copper plated layer
12
is used as an electrical feed layer.
Next, a layer of etching resist
18
is formed on the electrolytic copper plated layer
16
as shown in Step (d) of FIG.
6
. Examples of the layer of etching resist
18
are layers of plated solder and tin.
Next, the layer of plated resist
14
is removed as shown in Step (e) of FIG.
6
.
Next, the exposed electroless copper plated layer
12
is removed by using an etching solution as shown in Step (f) of FIG.
6
. In this case, an alkali etching solution is used as the etching solution.
Finally, the layer of etching resist
18
is removed from the electrolytic copper plated layer
16
. Due to the foregoing, a conductor pattern
20
, in which the electrolytic copper plated layer
16
is laminated on the electroless copper plated layer
12
, can be formed on the insulating layer
10
of the wiring board.
However, the above conventional method of forming a conductor pattern on a wiring board is disadvantageous as shown by the following. In the above method of forming a conductor pattern on a wiring board, an alkali etching solution is used as the etching solution for removing the electroless copper layer
12
. Therefore, not only the layer of electroless copper plating but also the layer of electrolytic copper plating is etched. Therefore, in order to prevent the thickness of the electrolytic copper plated layer
16
, which mainly composes the conductor pattern
20
, from being reduced, the layer of etching resist
18
, which is a protective film for protecting the electrolytic copper plated layer
16
from the etching solution, is formed on the electrolytic copper plated layer
16
. In this case, the processes of forming and removing the layer of etching resist
18
are indispensable. Accordingly, the process of forming the conductor pattern becomes complicated.
Even when the layer of etching resist
18
is formed on the electrolytic copper plated layer
16
, as long as the alkali etching solution is used as the etching solution, side portions of the electrolytic copper plated layer
16
, which are not covered with the layer of etching resist
18
, are etched, and the width of the electrolytic copper plated layer
16
is reduced. For the above reasons, it is conventional that the electrolytic copper plated layer
16
, the width of which is larger than the width of the target conductor pattern
20
, is formed while consideration is given to the above reduction of the width of the electrolytic copper plated layer
16
. According to the above conventional method, the width of the electrolytic copper plated layer
16
must be formed to be wider than the width of the target conductor pattern
20
. Accordingly, it is impossible to reduce an interval (gap) between the conductor patterns
20
to a limit of resolution of the plated resist
14
.
SUMMARY OF THE INVENTION
The present invention has been accomplished to solve the above problems. It is an object of the present invention to provide a method of forming a conductor pattern on a wiring board characterized in that: a conductor pattern forming process on the wiring board can be simplified; and an interval between the conductor patterns can be further reduced by suppressing the etching conducted on the side portions of the electrolytic copper plated layer.
The present invention provides a method of forming a conductor pattern of a wiring board, said method comprising the steps of: forming an electroless copper plated layer on a surface of an insulating layer; forming and patterning a layer of resist on the electroless copper plated layer; forming an electrolytic copper plated layer on the electroless copper plated layer exposed from the layer of patterned resist; removing the layer of resist for exposing the electroless copper plated layer except for a portion in which the electrolytic copper plated layer is formed; and removing the exposed electroless copper plated layer by using an etching solution composed of a mixed aqueous solution containing sulfuric acid, hydrogen peroxide and Cu chelate agent.
According to the above method, it is possible to selectively etch the electroless copper plated layer because the etching rate of electroless copper plating is greatly different from the etching rate of electrolytic copper plating due to a difference in the crystallizing condition between electroless copper plating and electrolytic copper plating in an etching solution composed of a mixed aqueous solution containing sulfuric acid, hydrogen peroxide and Cu chelate agent. For the above reasons, it is unnecessary to provide a layer of etching resist for protecting the electrolytic copper plated layer from the etching solution. Therefore, it is possible to omit the processes of forming and removing the layer of etching resist. Therefore, the entire process of forming the conductor pattern can be simplified. Further, there is no possibility of fluctuation of the width and thickness of the electrolytic copper plated layer. Accordingly, it is possible to set the thickness and width of the electrolytic copper plated layer to the thickness and width of the target conductor pattern even at the beginning of setting. Therefore, it is possible to form a conductor pattern, the gap of which is reduced to the limit of resolution of the resist.
When a step of annealing is provided, in which heat treatment is conducted on the electrolytic copper plated layer before the electroless copper plated layer is removed, a difference in the crystallizing condition between electroless copper plating and electrolytic copper plating is further extended, and a difference in the etching rate is extended. Consequently, it becomes possible to etch the electroless copper plated layer more selectively. Due to the foregoing, a quantity of etched electrolytic copper plated layer can be further reduced. Therefore, it becomes possible to form a finer conductor pattern.


REFERENCES:
patent: 4686015 (1987-08-01), Samuels et al.
patent: 5108786 (1992-04-01), Bayes
patent: 6054061 (2000-04-01), Bayes et al.
patent: 62-115893 (1987-05-01), None

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