Coating processes – Electrical product produced – Wire conductor
Reexamination Certificate
2001-03-21
2002-02-19
Talbot, Brian K. (Department: 1762)
Coating processes
Electrical product produced
Wire conductor
C427S097100, C427S282000, C427S123000, C427S126100, C101S127000, C101S129000
Reexamination Certificate
active
06348233
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to multi-layer ceramic (MLC) substrates and, more specifically, to conductive line features and methods for printing such features to enhance reliability of MLC substrates.
BACKGROUND OF THE INVENTION
Multi-layer ceramic (MLC) substrates, such as are used for chip carriers, comprise a number of discrete ceramic sheets laminated and sintered together. Each sheet has conductive lines printed on its surface with a conductive substance such as a metal, for example, copper paste. Holes punched through the ceramic sheet before sintering of the sheet (the unsintered sheet is known in the art as a “green” sheet) are filled with the conductive paste to provide conductive connections or “vias” between layers of the substrate. Thus, for example, a chip mounted on a completed MLC substrate is electrically connected to an underlying circuit board through the lines and vias of the MLC. Reliable connections in the MLC are critical to achieving the expected performance of the chip; the reliability of the connections is highly dependent upon the integrity of the line-to-via junctions.
Typically, the manufacture of such MLC substrates starts with a glass ceramic powder that is formed into a slurry and cast into a large sheet similar to how a sheet of paper is made. The large cast sheet is then dried and cut into smaller blanks. Via holes are punched into the blanks, and the lines are screen printed onto the blanks using masks and a conductive paste. Then, the layers of the MLC are stacked together and laminated in a press, cut to size, and sintered in an oven to create a homogenous ceramic substrate. One or more terminal plating steps may then be performed, including attaching one or more layers of thin film interconnects on top of the substrate, before joining the chip to the substrate.
Referring now to
FIG. 1
, there is shown a typical mask
10
known in the art and used to print the conductive lines on the green sheet blanks. Mask
10
comprises line patterns
12
and
13
each having a rectangular base section
14
with a width w
l
connected a to circular “cap” section
16
with a diameter d
c
. Circular cap section
16
is intended to be aligned with a hole punched in the blank, such that the paste flows down into the hole, creating a conductive via. Line pattern
12
has a “jogged” end
15
that is at an angle, typically 90° or 135°, to rectangular base section
14
.
Referring now to
FIG. 2
, there is shown a cross section of a line-to-via connection
20
on a green sheet blank
22
as manufactured using a mask of the prior art such as mask
10
shown in FIG.
1
. One known problem, which may be encountered in the creation of such MLC substrates, is that the mask may be misaligned with blank
22
such that the hole punched in the blank for the via
27
is not perfectly centered underneath cap section
16
on mask
10
(shown in FIG.
1
). In such case, line-to-via connection
20
between conductive line
24
and conductive via
27
may comprise a necked region
28
within the cap
29
.
Cap diameter d
c
is typically greater than via diameter d
v
and greater than width w
l
. For example, line
24
may have a width (w
l
in
FIG. 1
) of about 0.071 mm (2.8 mils), via
27
may have a diameter d
v
of about 0.089 to about 0.1 mm (about 3.5 to about 4 mil s), and cap
29
may have a diameter dc of about 0.114 to about 0.127 mm (about 4.5 to about 5 mils), whereas the alignment capabilities of the mask to the blank may only provide alignment of the cap to the via within an accuracy of about 0.05 mm (2 mils). Necked region
28
comprises an area having a thickness t
2
that is less than the thickness t
1
of the remainder of line
24
. This thinner area is subject to concentrated thermal fatigue stresses during normal operation of the chip, and may be susceptible to cracking, causing a major reliability problem for the MLC package.
SUMMARY OF THE INVENTION
To achieve this and other objects, and in view of its purposes, the present invention provides a method for minimizing formation of cracks at junctions between conductive vias and conductive lines in line-to-via connections on a substrate. Each line has a base section and a cap. Each cap is positioned over a via in the substrate, the cap diameter being greater than the via diameter.
The method comprises screen printing the conductive lines onto the substrate with conductive paste using a mask that provides a transition zone connected between the base section and the cap. The transition zone provides a volume of conductive paste during printing that is greater than the volume provided by the base section being directly connected to the cap. In particular, the transition zone volume is an effective amount to prevent necking of the conductive lines into the vias when the mask is misaligned to the substrate within an expected alignment tolerance. In one embodiment, the method comprises providing the transition zone with a greater width than the width of the base section.
The invention thus also comprises an improvement in standard conductive line-to-via connections. A standard conductive line-to-via connection comprises a conductive line connected to a conductive via having a via diameter. The standard conductive line has a base section with a first width and a cap with a cap diameter greater Than the via diameter and greater than the first width. The improvement comprises the conductive line having a transition zone between the base section and the cap, the transition zone having a second width greater than the first width. The transition zone may comprise a jogged end extending from the base section to the cap at an angle to the line, or a flared end extending from the base section.
The invention also comprises a line pattern in a screen printing mask for forming such a conductive line on a substrate. The line comprises a base section, a cap adapted to be positioned over a via in the substrate, and a transition zone connected between the base section and the cap. The line pattern has a cap shape adapted to print the cap, a base section shape adapted to print the base section, and a transition shape connected between the base section and the cap and adapted to print a transition zone connected between the base section and the cap. The cap shape has a cap diameter greater than the via diameter. The transition shape has a width greater than the width of the base section shape. The present invention also comprises a screening mask having such a line pattern.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
REFERENCES:
patent: 4323593 (1982-04-01), Tsunashima
patent: 4521262 (1985-06-01), Pellegrino
patent: 4543715 (1985-10-01), Ladarola et al.
patent: 4551789 (1985-11-01), Schettler et al.
patent: 4803110 (1989-02-01), Ahn et al.
patent: 5359928 (1994-11-01), Blessington et al.
patent: 5431332 (1995-07-01), Kirby et al.
patent: 5704535 (1998-01-01), Thompson, Sr.
patent: 5742009 (1998-04-01), Hamzehodoost et al.
patent: 5761803 (1998-06-01), St. John et al.
patent: 5784262 (1998-07-01), Sherman
patent: 5875102 (1999-02-01), Barrow
patent: 5888584 (1999-03-01), Visser-Bartelds et al.
Brody Jeffrey A.
Cox Harry D.
Garant John
Liu Hsichang
McLaughlin Paul G.
International Business Machines - Corporation
Ira D. Blecker, Esq.
Ratner & Prestia
Talbot Brian K.
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