Method of forming conductive bumps on a semiconductor device usi

Details Method of forming conductive bumps on a semiconductor device usi Method of forming conductive bumps on a semiconductor device usi

1994-12-01

1996-07-16

Fourson, George

Fishing, trapping, and vermin destroying

437228, 437948, 437962, 22818022, H01L 21285, H01L 21321

Patent

active

055366775

ABSTRACT:
A method for forming conductive bumps (60, 62) on a semiconductor device (50) using a mask structure (20) employs two masks (22, 24) individually fabricated and positioned in a back-to-back relationship. Each mask is patterned and isotropically etched to form a plurality of tapered openings (30, 40) corresponding to a pattern of terminal pads (54) on the semiconductor device. Metal is evaporated through the openings and onto the terminal pads. The mask structure is removed and the remaining metal is reflowed to form the conductive bumps. Using a mask structure having two individual masks (each with a thickness of one-half a typical mask thickness) enables smaller openings to be etched in each mask. Upon joining the two masks, the effective aspect ratio of the mask structure is reduced to produce smaller and denser conductive bumps without loss of volume and height control.

REFERENCES:
patent: 4334349 (1982-06-01), Aoyama et al.
patent: 4353935 (1982-10-01), Symersky
patent: 4895811 (1990-01-01), Inoue
patent: 5219117 (1993-06-01), Lin
patent: 5268068 (1993-12-01), Cowell et al.
"Process for Forming a High-Aspecfratio Solder Wterconnection"; IBM TDB, vol. 32, No. 6B, Nov. 1989, p. 180.
Motorola; C4 Product Design Manual; vol. 1: Chip and Wafer Design; Chapter 8--Bump Mask Design; pp. 8-1--8-2 (1992).
R. Tummala, et al.; IBM; Microelectronics Packaging Handbook; Ch. 6.3: Controlled Collapse Chip Connection (C4); pp. 366-391 (1989).

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