Method of forming closely spaced device regions utilizing select

Details Method of forming closely spaced device regions utilizing select Method of forming closely spaced device regions utilizing select

1979-05-25

1981-09-15

Dean, R.

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

29579, 29580, 148 15, 148187, 156647, 156648, 156657, 156662, 357 50, 357 55, 357 20, 357 35, H01L 2120, H01L 21302

Patent

active

042895502

ABSTRACT:
A semiconductor structure is provided by forming an isolation region in a portion of a semiconductor layer, forming a doped region in the semiconductor layer adjacent the isolation region, such doped region having a conductivity type opposite the conductivity type of the semiconductor layer, selectively masking a surface of the semiconductor layer exposing a portion of the doped region adjacent to the isolation region, and selectively etching the exposed portions of the adjacent doped region forming a depression having converging side walls separated from the isolation region by portions of the doped region. The semiconductor layer is an epitaxial layer providing the collector region of a transistor. The bottom portion of the depression is lightly doped to provide an active base region for the transistor. The active base region is electrically connected to the base contact through the more heavily doped region formed in the semiconductor layer. A doped polycrystalline silicon layer is formed over the bottom portion of the depression in contact with the active base region to provide an emitter contact for the transistor.

REFERENCES:
patent: 3083441 (1963-04-01), Little et al.
patent: 3648125 (1972-03-01), Peltzer
patent: 3755001 (1973-08-01), Kooi et al.
patent: 3783047 (1974-01-01), Paffen et al.
patent: 4066473 (1978-01-01), O'Brien
patent: 4110779 (1978-08-01), Rathbone et al.
patent: 4115797 (1978-09-01), Hingarh et al.
patent: 4155783 (1979-05-01), Feist
patent: 4168999 (1979-09-01), Vora et al.

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