Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1998-04-20
2000-02-01
Niebling, John F.
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438296, 438297, 438526, H01L 2176, H01L 21336
Patent
active
060202513
ABSTRACT:
A method is provided for use in a semiconductor fabrication process to form buried diffusion junctions in conjunction with shallow-trench isolation (STI) structures in a semiconductor device. This method features beak-like oxide layers formed to serve as a mask prior to the forming of the STI structures, which can prevent the subsequently formed buried diffusion junctions from being broken up during the process for forming the STI structures. Moreover, sidewall-spacer structures are formed on the sidewalls of a silicon nitride layer used as a mask in the ion-implantation process. This can prevent short-circuits between the buried diffusion junctions when the doped areas are annealed to be transformed into the desired buried diffusion junctions.
REFERENCES:
patent: 5763309 (1998-06-01), Chang
patent: 5946577 (1999-08-01), Tanaka
patent: 5960284 (1999-09-01), Lin et al.
Peng Nai-Chen
Yang Ming-Tzong
Ghyka Alexander G.
Niebling John F.
United Silicon Incorporated
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