Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating selected area
Reexamination Certificate
2000-02-11
2002-07-02
Valentine, Donald R. (Department: 1741)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Coating selected area
C205S096000, C205S123000, C205S148000, C205S170000, C205S224000, C205S226000, C205S228000
Reexamination Certificate
active
06413404
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming bumps and a device for metal plating.
2. Description of the Related Art
As a method of connecting semiconductor chips with a substrate, there are known a wire bonding method, a TAB method and a flip-chip connecting method.
Since the flip-chip connecting method satisfies a demand for an increased number of connecting pin points and a decreased the signal propagation delay time, it has gradually come into wide use. Especially, because the flip-connecting method, in which solder bumps are used, is capable of forming a large number of connections all at once, it has come into very wide use. Examples of bump forming methods for connecting the flip-chips are: the electrical plating method, the vapor deposition method, and the stud bump forming method conducted by wire bonding.
It is advantageous to use the electrical plating method because it is simple and the cost is low.
Conventionally, when bumps are formed by the electrical plating method, the following method is adopted.
First, a metallic layer made of an under-barrier-metal such as Ti/Cu, Cr/Cu and Cr/Ni is formed all over a wafer, on which wiring of a circuit used for a large number of chips has already been provided, by means of sputtering or non-electrolytic plating.
A liquid photo-resist is coated on the metallic layer several times, so that a resist layer, the thickness of which is approximately 50 &mgr;m, is formed. When this resist layer is processed by means of photolithography, fine holes are formed on the resist layer, so that a portion of the metallic layer on which bumps are formed can be exposed.
Then, solder bumps are formed on the metallic layer by the electrical plating method.
Next, the resist layer is removed and the under-barrier metal, except where the bumps are formed, is removed by means of etching.
FIG. 11
is an arrangement view showing an electrical plating device commonly used for the above electrical plating method.
Reference numeral
10
is an outer tank, and reference numeral
12
is a cup facing upward. Reference numeral
14
is an anode plate horizontally arranged in a lower portion of the cup
12
. Reference numeral
16
is a plating solution jet pipe which penetrates the outer tank
10
and the anode plate
14
, and an end of the plating solution jet pipe is open to the lower portion of the cup
12
. Reference numeral
18
is a holding jig capable of holding a wafer
20
while it is electrically connected with the wafer
20
. As can be seen in the drawing, the holding jig
18
is arranged at an open portion of the cup
12
while the surface of the wafer
20
to be plated is set downward. This holding jig
18
is also used as a cathode.
As shown in the drawing, the plating solution is fed from the jet pipe
16
into the cup
12
and further jets out toward the surface of the wafer
20
to be plated. When both electrodes are energized with electric current, bumps can be formed as described before.
The plating solution overflows from a gap formed between the holding jig
18
and the brim of the cup
12
and drops into the outer tank
10
. After that, the plating solution returns to the tank via the discharge pipe
22
.
FIG. 12
is a view showing a profile of the bump
24
formed by the above electrical plating device.
In this connection, when the bumps are formed by the above conventional electrical plating method, the following problems may be encountered.
In the above electrical plating device, plating is conducted as follows. An 8 inch diameter wafer, having a large number of fine holes, for example, about 400,000 fine holes, is attached to the electrical plating device while the wafer is set downward, and the plating solution is jetted onto the wafer from a lower portion. Due to the above arrangement, air tends to remain in the fine holes. As a result, there are holes in which plating is not conducted at all or plating is conducted insufficiently. Therefore, the product yield is deteriorated. Especially, in the case of a wafer, it is sized so that it can be formed into small narrow chips. Accordingly, the product yield of semiconductor chips is further deteriorated.
One reason for the occurrence of variation in the formation of a plating layer is a difference in the flow rate of the plating solution between the center and the periphery. Since the brim of the cup
12
is open to the outer tank
10
, the flow rate of the plating solution on the peripheral part, which overflows into the outer tank
12
of low resistance, is higher than the flow rate of the plating solution on the central part. Due to the foregoing, the thickness of the plating layer on the central part tends to be larger than that on the peripheral part.
Conventionally, it is impossible to form a plating layer of large thickness because the holes are fine in the case of a wafer. In order to solve the above conventional problem, a resist layer, the thickness of which is approximately 50 &mgr;m, is formed, and the solder bump 24 is formed into a mushroom shape as shown in
FIG. 12
so that a lack of height and quantity can be made up.
However, when the solder bump
24
is formed into a mushroom shape, the diameter of the solder bump
24
is increased. In accordance with an increase in the diameter, it becomes difficult to form a pattern densely, which is opposite to the demand for an increased number of pins. Further, an upper portion of the mushroom-shaped bump tends to collapse. Therefore, it is difficult for the mushroom-shaped bumps to be subjected to the KGD (Known Good Die) electrical continuity test in which the bumps are pressed against the inspection wiring so as to check the electrical continuity.
Since the diameter of the solder bump is changed in the process of electric plating, that is, the diameter of the solder bump is gradually increased in the process of electric plating, a change is caused in the density of electric current. Therefore, in the case of solder plating, there is a possibility that the composition of solder is changed. For this reason, it is necessary to adjust the density of electric current to be constant, which is troublesome, and further it becomes necessary to provide an expensive device to adjust the density of electric current.
SUMMARY OF THE INVENTION
The present invention has been accomplished to solve the above problems. It is an object of the present invention to provide a method of forming solder bumps by which air can be easily discharged and uniform, excellent solder bumps can be formed. Also, it is an object of the present invention to provide a plating device preferably used for the method of forming solder bumps.
In order to accomplish the above object, the present invention is composed as follows.
The present invention is to provide a method of forming bumps comprising the steps of: forming a metallic layer of under-barrier-metal on a surface of an object to be plated such as a semiconductor chip; forming a resist layer on the metallic layer; exposing a portion of the metallic layer, in which bumps of the semiconductor chip are formed, by forming fine holes on the resist layer; dipping the object to be plated, which is held by a holding jig, in a plating solution substantially vertically or obliquely so that the surface of the object to be plated can be directed upward while being opposed to an anode plate after the object to be plated is held by the holding jig and the object is electrically connected with the holding jig; forming bumps in the fine holes on the metallic layer by energizing an electrode with electric current while the plating solution is being jetted against the surface to be plated from a nozzle having a nozzle section which is opposed to the surface of the object to be plated; removing the resist layer; and removing the metallic layer except where the bumps are formed.
According to the method described above, fine holes are directed in the lateral direction or the upward direction, and further the plating solution is jetted out in a direction perpendicular to
Ihara Yoshihiro
Kanazawa Takeo
Kobayashi Tsuyoshi
Leader William T.
Pennie & Edmonds LLP
Shinko Electric Industries Co. Ltd.
Valentine Donald R.
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