Method of forming bipolar transistor salicided emitter using...

Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Radiation or energy treatment modifying properties of...

Reexamination Certificate

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C438S365000

Reexamination Certificate

active

06468871

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fabrication of semiconductor integrated circuit structures and, in particular, to the utilization of selective laser annealing to form a uniformly salicided crystalline silicon emitter in a bipolar transistor structure.
2. Discussion of the Related Art
FIG. 1
illustrates several problems resulting from the formation of the emitters of bipolar transistors utilizing conventional integrated circuit fabrication techniques. First, variations in the vertical thickness of the emitter polysilicon film in the emitter window cause non-uniform doping of the emitter poly; this results in a non-uniform doping profile in the emitter region when ion implantation is used, which causes process non-uniformity and, therefore, device performance variations. Second, incomplete filling of the emitter window with emitter polysilicon creates voids, resulting in a non-uniform emitter/base contact interface due to emitter narrowing; this leads to a smaller and non-reproducible emitter/base junction interfacial area. Third, insufficient dopant activation using conventional annealing techniques results in lower current gain in the bipolar device.
SUMMARY OF THE INVENTION
The present invention utilizes selective laser recrystallization of emitter polysilicon for the formation of uniform emitter/base junctions and highly uniformly doped emitter electrodes using conventional ion implant doping and polysilicon deposition techniques. The laser recrystallization step converts the polysilicon into single crystal silicon which facilitates formation of a uniform refractory metal silicide on top of the emitter. A uniform silicide layer reduces emitter resistance and, therefore, enhances the bipolar transistor performance.
Thus, the present invention is directed to a method of forming a salicided crystalline silicon emitter structure in a semiconductor integrated circuit bipolar transistor. The bipolar transistor structure includes a collector region of a first conductivity type formed in a semiconductor substrate and a base region of a second conductivity type, opposite the first conductivity type, formed in the collector region. A layer of dielectric material is formed on the surface of the base region. An emitter window is then opened in the dielectric material to expose a surface area of the base region. Polysilicon is then formed over the layer of dielectric material and extending into the emitter window such that at least a portion of the polysilicon layer is in contact with the surface area of the base region. Dopant of the first conductivity type is then introduced into the polysilicon. A region of anti-reflective coating (ARC) material, preferably silicon nitride, is formed on the doped polysilicon layer over the emitter window opening such that portions of the polysilicon layer are exposed. Sufficient laser energy is then applied to the structure resulting from the foregoing steps to cause the polysilicon underlying the region of ARC material to melt and flow and recrystallize. Unwanted portions of the laser annealed polysilicon are then removed by wet etching or dry etching, in the presence of the ARC material, which serves as a hard mask. Thus, the ARC material is used to define a single crystal silicon emitter region that extends into the emitter window opening and is in interfacial contact with the surface area of the base region. The ARC material is then removed and conventional techniques are utilized to form a layer of refractory metal silicide on the top surface of the single crystal silicon emitter.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized.


REFERENCES:
patent: 4407060 (1983-10-01), Sakurai
patent: 4651410 (1987-03-01), Feygenson
patent: 5933720 (1999-08-01), Yokoyama et al.

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