Method of forming bipolar transistor having closely spaced devic

Details Method of forming bipolar transistor having closely spaced devic Method of forming bipolar transistor having closely spaced devic

1989-06-29

1991-11-12

Chaudhuri, Olin

Fishing, trapping, and vermin destroying

437200, 437984, 437 57, 148DIG19, 148DIG10, H01L 21331

Patent

active

050647733

ABSTRACT:
A method of forming a bipolar transistor. A base region is implanted into an epitaxial layer. An emitter and collector contact regions are formed of doped polysilicon on the epitaxial layer, the emitter being formed over the base region. The implant is below the surface of the epitaxial layer in all regions not covered by the collector region. Low resistance silicide contacts, such as titanium or cobalt, are formed on the structure in a self-aligned fashion. This method is well suited for forming BJTs as part of BiCMOS circuits.

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