Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2001-01-04
2003-04-01
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
68, 68
Reexamination Certificate
active
06541857
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to Ball Grid Array (hereinafter “BGA”) packages. More particularly, the present invention relates to a method of forming interconnections having mixed solder joint profiles within BGA packages to increase fatigue life of the BGA interconnections.
2. Related Art
In the manufacture of BGA packages, differences in the coefficients of thermal expansion between a chip carrier or module and a board creates stresses, in particular, shear stress, within the interconnections, or solder joints. The stresses are typically the highest in the solder joints at the corners of the BGA package, and in the solder joints directly beneath the corners and edges of the chip. Frequently, the solder joints in these regions cannot withstand the stresses applied over many on/off cycles, resulting in fatigue failure of the BGA solder joints. It is well known that elongating the solder joints will extend the fatigue life. It was determined that elongated solder joints are more compliant and have lower shear stress than when compared to shorter solder joints having the same volume.
Several techniques have been used in the industry to produce elongated solder joints. For instance, spacers, high-melt solder columns, and other additional materials, have been placed between the module and the board to force the solder joints to elongate. Lifting forces have been applied to the BGA packages during solidification to extend the solder joints. Solder joints having increased volume have been placed at selected locations within the package thereby forcing the other solder joints to elongate, and so on.
However, some of these techniques are incompatible with the trend toward reducing the size of semiconductor packages. Other techniques entail a complicated assembly process which increases manufacturing costs and reduces production yields. Further, some techniques decrease the space on the substrate available for wiring.
Accordingly, there exists a need in the industry for a BGA package exhibiting an increased fatigue life, without increasing the pad size, solder volume, size of the board, etc., or raising the costs.
SUMMARY OF THE INVENTION
The present invention provides a method of forming BGA interconnections, or solder joints, using a combination of mask-defined and pad-defined solder joints to increase fatigue life of the solder joints. In particular, pad-defined solder joints lack the stress concentrations found within the mask-defined solder joints. Therefore, pad-defined solder joints are selectively placed in regions of high stress, particularly at the corners of the BGA package, and directly below the corners and edges of the chip. Mask-defined solder joints are located throughout the remainder of the BGA package to increase the equilibrium height of the pad-defined solder joints, thereby making the pad-defined solder joints more compliant.
The first general aspect of the present invention provides a method of forming Ball Grid Array (BGA) interconnections, comprising the steps of: providing a first substrate and a second substrate, each having a plurality of conductive pads mounted thereon; and applying a first mask to the first substrate and a second mask to the second substrate, wherein a first plurality of openings of the first and second masks expose selected conductive pads and have a diameter larger than a diameter of the conductive pads, and a second plurality of openings of the first and second masks expose selected conductive pads and have a diameter smaller than a diameter of the conductive pads. This aspect allows for a plurality of mask-defined solder joints designed to increase the equilibrium height of pad-defined solder joints. Further, this aspect selectively positions elongated pad-defined solder joints, having no stress concentrations therein, at the high stress regions of the BGA package, thereby increasing the fatigue life of the package.
The second general aspect of the present invention provides a semiconductor package having a series of Ball Grid Array (BGA) interconnections, wherein a plurality of the BGA interconnections are pad-defined solder joints and a plurality of the BGA interconnections are mask-defined solder joints. This aspect allows for similar advantages as those associated with the first aspect.
The third general aspect of the present invention provides a method of forming Ball Grid Array (BGA) interconnections having mixed solder profiles, comprising the steps of: providing a first substrate and a second substrate; applying a mask to at least one of the first and second substrates, wherein a plurality of openings in the mask produces pad-defined solder joints and a plurality of openings in the mask produces mask-defined solder joints. This aspect provides similar advantages as those mentioned with respect to the first aspect.
The fourth general aspect of the present invention provides a substrate having a series of Ball Grid Array (BGA) interconnections, wherein a plurality of the BGA interconnections are pad-defined solder joints and a plurality of the EGA interconnections are mask-defined solder joints. This aspect provides similar advantages as those mentioned with respect to the first aspect.
The fifth general aspect of the present invention provides a solder mask, adapted to be coupled to a substrate having conductive pads thereon, the solder mask having a first plurality of openings and a second plurality of openings, wherein the first plurality of openings are larger than the conductive pads and the second plurality of openings are smaller than the conductive pads. This aspect provides similar advantages as those mentioned with respect to the first aspect.
The foregoing and other features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention.
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Caletka David V.
Johnson Eric A.
Fraley Lawrence R.
Lee Eddie
Lee Eugene
Schmeiser Olsen & Watts
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