Method of forming asymmetric wells for DRAM cells

Details Method of forming asymmetric wells for DRAM cells Method of forming asymmetric wells for DRAM cells

2000-06-12

2002-04-30

Bowers, Charles (Department: 2823)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S238000, C438S239000, C438S253000, C438S381000, C257S298000, C257S306000

Reexamination Certificate

active

06380045

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention:
The present invention relates to a fabrication method for forming asymmetric wells of a DRAM cell, and more particularly to a fabrication method for producing a transistor that is capable of reducing body effect, gate-swing and junction leakage current so as to enhance the reliability of a DRAM device.
2. Description of the Prior Art:
As the function of a microprocessor is becoming more and more powerful and the operation scale of computer programs is becoming larger and larger, the demand for increasing the memory capacity of a memory storage device grows substantially. In order to fabricate low-cost memory devices with high memory capacity, DRAM technology becomes the leading-edge driver to push the semiconductor manufacturing technology to a higher level of integration. Attributed to 1T1C (1-Transistor, 1-Capacitor) structure adoped by DRAM cell higher integration level relative to other types of memory devices can be realized. The size of a transistor in a DRAM cell is therefore shrunk to increase the level of integration in a DRAM device. However, when the size is reduced to a sub-micron level, short channel effect, or SCE, can become very serious as a phenomenon of punchthrough can easily occur.
Referring to
FIG. 1
, it shows the cross-sectional view of a transistor used for solving the above-mentioned mentioned problems according to a conventional method. The method involves increasing the dosages of implants in a P well
102
and/or an anti-punchthrough region
104
formed in the entire active area of a silicon semiconductor substrate
100
. A detailed description is as follows. A photoresist is formed over a silicon semiconductor substrate
100
by using a well mask before the N type transistors
106
of a DRAM device is formed. An ion implant process is then employed which uses the photoresist as an implant mask to form the P well
102
and the anti-punchthrough region
104
in sequence. Although the increases of the dosages of implants in the P well
102
and/or the anti-punchthrough region
104
can relieve the aforementioned short channel effect, it nevertheless leads to increases in the body effect, gate-swing, and junction leakage in a substrate
100
, all of which are detrimental to DRAM cell's charge retention. Besides, the increase in body effect can degrade write-back efficiency, or less charges will be available for sensing. The increase in gate-swing can lead to the rise in I
off
, which is a major cause for disturb failure. The increase in junction leakage can aggravate decay of the sensing signal during each refresh cycle.
Furthermore, scaling down the thickness of a gate oxide layer can be the most straightforward way to reduce body effect and gate-swing; however, the improvement will eventually saturate due to the limitations set by the finite thickness of an inversion layer. If the thickness of the gate oxide layer is overly scaled down, a tunneling current due to the Fowler-Nordheim effect or direct tunneling will occur. Fabricating DRAM devices on a SOI substrate is another way to minimize body effect and gate-swing without resort to scaling down the thickness of gate oxide layers. However, this new technology is not yet mature for practical use in DRAM production.
Therefore, it is an object of the present invention to provide a fabrication method for forming asymmetric wells of a DRAM cell in order to reduce the body effect, gate-swing, and junction leakage current found in a substrate so as to enhance DRAM cell's charge retention.
SUMMARY OF THE INVENTION
To achieve the above-mentioned objects, the method for forming asymmetric wells of a DRAM cell comprises: forming a gate structure on a substrate where a first well is formed thereupon; forming a first doped region and a second doped region on both sides of the gate structure in the first well to be used as a bit line contact region and a node contact region respectively; and then forming a second well below the bit line contact region, wherein the dopant concentration of the second well is higher than that of the first well.
According to an embodiment of the present invention, an anti-punchthrough pocket is formed below the first doped region in the second well after the second well is formed.
Inasmuch as the local second well and the local anti-punchthrough pocket do not expand to the node contact region, body effect, gate-swing, and junction leakage are reduced to improve DRAM cell's charge retention.


REFERENCES:
patent: 5712201 (1998-01-01), Lee et al.
patent: 5744387 (1998-04-01), Tseng
patent: 6087690 (2000-07-01), Chi

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