Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of...
Reexamination Certificate
2001-02-12
2002-12-10
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
C438S322000, C438S350000, C438S364000, C438S202000, C438S313000
Reexamination Certificate
active
06492237
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor processing, and in particular, to a method of forming an NPN semiconductor device using an oxide-nitride-oxide (ONO) layers for emitter formation and another implementation using a local oxidation of silicon (LOCOS) for emitter formation.
BACKGROUND OF THE INVENTION
A typical NPN semiconductor device comprises a collector region doped with n-doping material and formed within a substrate, a base region doped with p-doping material and formed over the collector region, and an emitter region doped with p-doping material and formed over the base region. The base and collector regions are typically wider than the emitter region. Accordingly, the sub-region of the base region directly under the emitter region is typically referred to as the intrinsic base region. Whereas the sub-region of the base region not directly under the emitter region is referred to as the extrinsic base region.
The characteristics and performance of a typical NPN semiconductor device is generally sensitive to the thickness of the intrinsic and extrinsic sub-regions of the base region. For example, the thickness of the intrinsic base sub-region typically affects the speed of the NPN device. A thinner intrinsic base sub-region typically results in higher speed capability for the NPN device. Whereas, a thicker intrinsic base sub-region typically results in lower speed capability for the NPN device. Also, the thickness of the extrinsic base sub-region typically affects the base resistance of the NPN device. A thinner extrinsic base sub-region typically results in higher base resistance for the NPN device. Whereas, a thicker extrinsic base sub-region typically results in lower base resistance for the NPN device.
Existing processes open the emitter window in oxide by means of highly selective (oxide to silicon) reactive ion etches. While etch selectivity is usually very high, it is not infinite. This results in a certain amount of the non-uniform (from device to device) base silicon erosion and, consequently, in devices with variable base width and poor repeatability.
Thus, to maintain repeatability of device performance from lot to lot and within wafer, there is a need for a method of forming an NPN device which provides an improved control of the thickness of the intrinsic and extrinsic base sub-regions. In addition, there is a need for a method of forming an NPN device which results in a thinner intrinsic base sub-region to improve the speed capability of the device. Furthermore, there is a need for a method of forming an NPN device which results in a thicker extrinsic base sub-region to achieve a relatively low base resistance for the device.
Such needs and others are met with the method of forming an NPN device in accordance with the invention.
SUMMARY OF THE INVENTION
An aspect of the invention relates to a method of forming an NPN semiconductor device that provides improved control of the thickness of the intrinsic and extrinsic base sub-regions, provides a thinner intrinsic base sub-region to improve the speed capability of the device, and provides a thicker extrinsic base sub-region to achieve a relatively low base resistance for the device.
The method of forming an NPN semiconductor device of the invention comprises forming a collector region within a substrate, forming a base region over the collector region, and forming an oxide-nitride-oxide stack over the base region. Once these three structures are formed, an opening is created through the oxide-nitride-oxide stack to expose the top surface of the base region. Then, a doped polysilicon material is used to fill the opening and make electrical contact to the base region. The use of the oxide-nitride-oxide stack with appropriate process to etch the opening eliminates the exposure of the base region to reactive ion etch environment typical of prior art methods for forming NPN semiconductor devices.
In the exemplary implementation of the method of forming an NPN semiconductor device, the forming of the oxide-nitride-oxide stack comprises thermally growing or depositing a 30 to 300 Angstrom layer of silicon dioxide (SiO
2
) over the base region, then depositing a 200 to 1000 Angstrom layer of silicon nitride (Si
3
N
4
) using either low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), or plasma enhanced chemical vapor deposition (PECVD), and depositing a 1000 to 5000 Angstrom layer of silicon dioxide (SiO
2
) by chemical vapor deposition.
The forming of the opening through the oxide-nitride-oxide stack comprises depositing a coat of photo resist over the oxide-nitride-oxide stack and forming a window through which etching is to take place. Then, the etching of the upper oxide layer is performed using an etching process that is highly selective to nitride. This is followed by etching of the nitride layer using an etching process that is highly selective to oxide. Finally, the etching of the lower oxide layer is performed using an etching process that is highly selective to silicon. Once the opening is formed, an in-situ doped or non-doped polysilicon material is deposited to fill the opening. The non-doped polysilicon is then doped to achieve a desired conductivity.
Another aspect of the invention is a variation of the above method of forming an NPN semiconductor device. This variation uses the same initial steps of the method described above, namely forming a collector region, forming a base region over the collector region, forming an oxide-nitride-oxide stack over the base region, and forming an opening through the oxide-nitride-oxide stack to expose the top surface of the base region. Once this is done, a local oxidation of silicon (LOCOS) is performed on the base region to form a silicon dioxide layer at the bottom of the opening. Then a central portion of the silicon dioxide layer is etched away to form oxide spacers on the side of the openings at the top surface of the base region. Then, polysilicon material is deposited to fill the opening and doped to achieve a desired conductivity.
Other aspects, features and techniques of the invention will become apparent to one skilled in the relevant art in view of the following detailed description of the invention.
REFERENCES:
patent: 4157269 (1979-06-01), Ning et al.
patent: 4871684 (1989-10-01), Glang et al.
patent: 4879255 (1989-11-01), Deguchi et al.
patent: 4980738 (1990-12-01), Welch et al.
patent: 5061652 (1991-10-01), Bendernagel et al.
patent: 5159429 (1992-10-01), Bendernagel et al.
patent: 5244821 (1993-09-01), Ham et al.
patent: 5320972 (1994-06-01), Wylie
patent: 5340753 (1994-08-01), Bassous
patent: 5515710 (1996-05-01), Boyd et al.
patent: 5804486 (1998-09-01), Zambrano et al.
patent: 5930635 (1999-07-01), Bashir et al.
patent: 6180442 (2001-01-01), Gris
patent: 6190984 (2001-02-01), Ryum et al.
patent: 6287930 (2001-09-01), Park
patent: 6376322 (2002-04-01), Gris
S. Wolf, Silicon Processing For The VLSI ERA, vol. 1, Lattin Press, 1986, pp. 191-194.
Kalnitsky Alexander
Park Sang Hoon
Scheer Robert F.
Blakely , Sokoloff, Taylor & Zafman LLP
Keshavan Belur V
Maxim Integrated Products Inc.
Smith Matthew
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