Method of forming an N+ poly-to- N+ silicon capacitor structure

Details Method of forming an N+ poly-to- N+ silicon capacitor structure Method of forming an N+ poly-to- N+ silicon capacitor structure

1988-03-11

1989-10-31

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 34, 437 57, 437 60, 437919, 437985, 148DIG163, 357 236, H01L 2194

Patent

active

048777510

ABSTRACT:
An N+ poly-to-N+ silicon capacitor structure is provided by adding a single mask step to a standard CMOS process flow. The capacitor oxide between the N+ poly plate and the N+ silicon plate is grown simultaneously with gate oxide for the MOSFET devices. A high dose, deep phosphorous implant is employed to form the N+ substrate plate. This results in an excellent capacitance voltage coefficient. The resulting thin interplate oxide leads to high capacitance per unit area and, thus, small die size.

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